CY7C66113C-XC CYPRESS [Cypress Semiconductor], CY7C66113C-XC Datasheet - Page 32

• Manufacturer Part Number: CY7C66113C-XC
• Description: Full-Speed USB (12 Mbps) Peripheral Controller with Integrated Hub
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-08024 Rev. *B
Global Interrupt Enable Register
Bit 0: USB Bus RST Interrupt Enable
Bit 1: 128- s Interrupt Enable
Bit 2: 1.024-ms Interrupt Enable
Bit 3: USB Hub Interrupt Enable
Bit 4: DAC Interrupt Enable
Bit 5: GPIO Interrupt Enable
Bit 6: I
Bit 7: Reserved.
USB Endpoint Interrupt Enable
Bit 0: EPA0 Interrupt Enable
Bit 1: EPA1 Interrupt Enable
Bit 2: EPA2 Interrupt Enable
Bit 3: EPB0 Interrupt Enable
Bit 4: EPB1 Interrupt Enable
Bit [7..5]: Reserved
During a reset, the contents the Global Interrupt Enable Register and USB End Point Interrupt Enable Register are cleared,
effectively, disabling all interrupts.
The interrupt controller contains a separate flip-flop for each interrupt. See Figure 16-3 for the logic block diagram of the interrupt
controller. When an interrupt is generated, it is first registered as a pending interrupt. It stays pending until it is serviced or a reset
occurs. A pending interrupt only generates an interrupt request if it is enabled by the corresponding bit in the interrupt enable
registers. The highest priority interrupt request is serviced following the completion of the currently executing instruction.
Bit #
Bit Name
Read/Write
Reset
Bit #
Bit Name
Read/Write
Reset
1 = Enable Interrupt on a USB Bus Reset; 0 = Disable interrupt on a USB Bus Reset (refer to section 16.3).
1 = Enable Timer interrupt every 128 s; 0 = Disable Timer Interrupt for every 128 s.
1= Enable Timer interrupt every 1.024 ms; 0 = Disable Timer Interrupt every 1.024 ms.
1 = Enable Interrupt on a Hub status change; 0 = Disable interrupt due to hub status change. (Refer to section 16.6.)
1 = Enable Interrupt on falling/rising edge on any GPIO; 0 = Disable Interrupt on falling/rising edge on any GPIO. (Refer to
sections 16.8, 9.1, and 9.2.)
1 = Enable Interrupt on I2C related activity; 0 = Disable I2C related activity interrupt. (Refer to section 16.9.)
1 = Enable Interrupt on data activity through endpoint A0; 0 = Disable Interrupt on data activity through endpoint A0.
1 = Enable Interrupt on data activity through endpoint A1; 0 = Disable Interrupt on data activity through endpoint A1.
1 = Enable Interrupt on data activity through endpoint A2; 0 = Disable Interrupt on data activity through endpoint A2.
1 = Enable Interrupt on data activity through endpoint B0; 0 = Disable Interrupt on data activity through endpoint B0.
1 = Enable Interrupt on data activity through endpoint B1; 0 = Disable Interrupt on data activity through endpoint B1.
1 = Enable DAC Interrupt; 0 = Disable DAC interrupt.
2
C Interrupt Enable
7
Reserved
-
-
7
Reserved
-
-
6
I
Enable
R/W
0
6
Reserved
-
-
2
C Interrupt
Figure 16-2. USB Endpoint Interrupt Enable Register
Figure 16-1. Global Interrupt Enable Register
5
GPIO Interrupt
Enable
R/W
0
5
Reserved
-
-
4
DAC Interrupt
Enable
R/W
0
4
EPB1 Interrupt
Enable
R/W
0
3
USB Hub
Interrupt
Enable
R/W
0
3
Enable
R/W
0
EPB0 Interrupt
2
1.024-ms
Interrupt
Enable
R/W
0
2
EPA2 Interrupt
Enable
R/W
0
R/W
1
128- s
Interrupt
Enable
0
1
EPA1 Interrupt
Enable
R/W
0
CY7C66013C
CY7C66113C
Page 32 of 61
ADDRESS 0X20
ADDRESS 0X21
0
USB Bus RST
Interrupt
Enable
R/W
0
0
EPA0 Interrupt
Enable
R/W
0
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