CY7C66113C-XC CYPRESS [Cypress Semiconductor], CY7C66113C-XC Datasheet - Page 36

• Manufacturer Part Number: CY7C66113C-XC
• Description: Full-Speed USB (12 Mbps) Peripheral Controller with Integrated Hub
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-08024 Rev. *B
16.9
The I
involves reading the I
I
subsequent transaction. The interrupt indicates that status bits are stable and it is safe to read and write the I
to Section 13.0 for details on the I
When enabled, the I
bits are in the I
The Continue/Busy bit is cleared by hardware prior to interrupt conditions 1 to 4. Once the Data Register has been read or written,
firmware should configure the other control bits and set the Continue/Busy bit for subsequent transactions. Following an interrupt
from master mode, firmware should perform only one write to the Status and Control Register that sets the Continue/Busy bit,
without checking the value of the Continue/Busy bit. The Busy bit may otherwise be active and I
changed by the hardware during the transaction, until the I
17.0
The USB hardware includes a USB Hub repeater with one upstream and four downstream ports. The USB Hub repeater interfaces
to the microcontroller through a full-speed Serial Interface Engine. An external series resistor of R
with all upstream and downstream USB outputs in order to meet the USB driver requirements of the USB specification. The
CY7C66x13C microcontroller can provide the functionality of a compound device consisting of a USB hub and permanently
attached functions.
17.1
The SIE allows the CY7C66x13C microcontroller to communicate with the USB host through the USB repeater portion of the hub.
The SIE simplifies the interface between the microcontroller and USB by incorporating hardware that handles the following USB
bus activity independently of the microcontroller:
Firmware is required to handle the following USB interface tasks:
17.2
The internal hub and any compound device function are enumerated under firmware control. The hub is enumerated first, followed
by any integrated compound function. After the hub is enumerated, the USB host can read hub connection status to determine
2
1. In slave receive mode, after the slave receives a byte of data: The Addr bit is set, if this is the first byte since a start or restart
2. In slave receive mode, after a stop bit is detected: The Received Stop bit is set, if the stop bit follows a slave receive transaction
3. In slave transmit mode, after the slave transmits a byte of data: The ACK bit indicates if the master that requested the byte
4. In master transmit mode, after the master sends a byte of data. Firmware should load the Data Register if necessary, and
5. In master receive mode, after the master receives a byte of data: Firmware should read the data and set the ACK and
6. When the master loses arbitration: This condition clears the MSTR MODE bit and sets the ARB Lost/Restart bit immediately
• Bit stuffing/unstuffing
• Checksum generation/checking
• ACK/NAK/STALL
• Token type identification
• Address checking.
• Coordinate enumeration by responding to SETUP packets
• Fill and empty the FIFOs
• Suspend/Resume coordination
• Verify and select DATA toggle values.
C Data Register as appropriate, and finally writing the Processor Status and Control Register (Figure 15-1) to initiate the
signal was sent by the external master. Firmware must read or write the data register as necessary, then set the ACK, Xmit
MODE, and Continue/Busy bits appropriately for the next byte.
where the ACK bit was cleared to 0, no stop bit detection occurs.
acknowledged the byte. If more bytes are to be sent, firmware writes the next byte into the Data Register and then sets the
Xmit MODE and Continue/Busy bits as required.
set the Xmit MODE, MSTR MODE, and Continue/Busy bits appropriately. Clearing the MSTR MODE bit issues a stop signal
to the I
Continue/Busy bits appropriately for the next byte. Clearing the MSTR MODE bit at the same time causes the master state
machine to issue a stop signal to the I
and then waits for a stop signal on the I
2
C interrupt occurs after various events on the I
I
USB Serial Interface Engine
USB Enumeration
2
2
USB Overview
C Interrupt
C-compatible bus and return to the idle state.
2
C Status and Control Register.
2
C-compatible state machines generate interrupts on completion of the following conditions. The referenced
2
C Status and Control Register (Figure 13-2) to determine the cause of the interrupt, loading/reading the
2
C registers.
2
C-compatible bus and leave the I
2
C-compatible bus to generate the interrupt.
2
C-compatible bus to signal the need for firmware interaction. This generally
2
C interrupt occurs.
2
C-compatible hardware in the idle state.
2
ext
C register contents may be
must be placed in series
CY7C66013C
CY7C66113C
2
C registers. Refer
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