CY7C66113C-XC CYPRESS [Cypress Semiconductor], CY7C66113C-XC Datasheet - Page 26

• Manufacturer Part Number: CY7C66113C-XC
• Description: Full-Speed USB (12 Mbps) Peripheral Controller with Integrated Hub
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-08024 Rev. *B
are set to ‘0’ when the device is suspended, that DAC input will float. The floating pin could result in excessive current consumption
by the device, unless an external load places the pin in a deterministic state.
DAC Port Data
Bit [1..0]: High Current Output 3.2 mA to 16 mA typical
Bit [7..2]: Low Current Output 0.2 mA to 1 mA typical
10.1
Each DAC I/O pin has an associated DAC Isink register to program the output sink current when the output is driven LOW. The
first Isink register (0x38) controls the current for DAC[0], the second (0x39) for DAC[1], and so on until the Isink register at 0x3F,
controls the current to DAC[7].
DAC Sink Register
Bit [3..0]: Isink [x] (x= 0..3)
Bit [7..4]: Reserved
10.2
A DAC port interrupt can be enabled/disabled for each pin individually. The DAC Port Interrupt Enable register provides this
feature with an interrupt enable bit for each DAC I/O pin. All of the DAC Port Interrupt Enable register bits are cleared to ‘0’ during
a reset. All DAC pins share a common interrupt, as explained in Section 16.7.
DAC Port Interrupt
Bit [7..0]: Enable bit x (x= 0..7)
As an additional benefit, the interrupt polarity for each DAC pin is programmable with the DAC Port Interrupt Polarity register.
Writing a ‘0’ to a bit selects negative polarity (falling edge) that causes an interrupt (if enabled) if a falling edge transition occurs
on the corresponding input pin. Writing a ‘1’ to a bit in this register selects positive polarity (rising edge) that causes an interrupt
(if enabled) if a rising edge transition occurs on the corresponding input pin. All of the DAC Port Interrupt Polarity register bits are
cleared during a reset.
DAC IO Interrupt Polarity
Bit #
Bit Name
Read/Write
Reset
Bit #
Bit Name
Read/Write
Reset
Bit #
Bit Name
Read/Write
Reset
Bit #
Bit Name
Read/Write
Reset
1= I/O pin is an output pulled HGH through the 14-k
1= I/O pin is an output pulled HGH through the 14-k
Writing all ‘0’s to the Isink register causes 1/5 of the max current to flow through the DAC I/O pin. Writing all ‘1’s to the Isink
register provides the maximum current flow through the pin. The other 14 states of the DAC sink current are evenly spaced
between these two values.
1 = Enables interrupts from the corresponding bit position; 0= Disables interrupts from the corresponding bit position
DAC Isink Registers
DAC Port Interrupts
7
DAC[7]
R/W
1
7
Reserved
-
7
Enable Bit 7
W
0
7
Polarity Bit 7
W
0
6
DAC[6]
R/W
1
6
Reserved
-
6
Enable Bit 6
W
0
6
Polarity Bit 6
W
0
Figure 10-5. DAC Port Interrupt Polarity
Figure 10-4. DAC Port Interrupt Enable
5
DAC[5]
R/W
1
5
Reserved
-
5
Enable Bit 5
W
0
5
Polarity Bit 5
W
0
Figure 10-3. DAC Sink Register
Figure 10-2. DAC Port Data
4
DAC[4]
R/W
1
resistor. 0 = I/O pin is an input with an internal 14-k pull-up resistor.
resistor. 0 = I/O pin is an input with an internal 14-k pull-up resistor.
4
Reserved
-
4
Enable Bit 4
W
0
4
Polarity Bit 4
W
0
3
DAC[3]
R/W
1
3
Isink[3]
W
0
3
Enable Bit 3
W
0
3
Polarity Bit 3
W
0
2
DAC[2]
R/W
1
2
Isink[2]
W
0
2
Enable Bit 2
W
0
2
Polarity Bit 2
W
0
R/W
1
DAC[1]
1
1
Isink[1]
W
0
1
Enable Bit 1
W
0
1
Polarity Bit 1
W
0
CY7C66013C
CY7C66113C
ADDRESS 0x38 –0x3F
Page 26 of 61
ADDRESS 0x30
0
DAC[0]
R/W
1
0
Isink[0]
W
0
0
Enable Bit 0
W
0
0
Polarity Bit 0
W
0
ADDRESS 0x31
ADDRESS 0x32
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