CY7C66113C-XC CYPRESS [Cypress Semiconductor], CY7C66113C-XC Datasheet - Page 22

• Manufacturer Part Number: CY7C66113C-XC
• Description: Full-Speed USB (12 Mbps) Peripheral Controller with Integrated Hub
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-08024 Rev. *B
The USB transmitter is disabled by a WDR because the USB Device Address Registers are cleared (see Section 19.1).
Otherwise, the USB Controller would respond to all address 0 transactions.
It is possible for the WDR bit of the Processor Status and Control Register (0xFF) to be set following a POR event. If a firmware
interrogates the Processor Status and Control Register for a set condition on the WDR bit, the WDR bit should be ignored if the
POR (bit 3 of register 0xFF) bit is set.
8.0
The CY7C66x13C can be placed into a low-power state by setting the Suspend bit of the Processor Status and Control register.
All logic blocks in the device are turned off except the GPIO interrupt logic and the USB receiver. The clock oscillator and PLL,
as well as the free-running and WDTs, are shut down. Only the occurrence of an enabled GPIO interrupt or non-idle bus activity
at a USB upstream or downstream port wakes the part from suspend. The Run bit in the Processor Status and Control Register
must be set to resume a part out of suspend.
The clock oscillator restarts immediately after exiting suspend mode. The microcontroller returns to a fully functional state 1 ms
after the oscillator is stable. The microcontroller executes the instruction following the I/O write that placed the device into suspend
mode before servicing any interrupt requests.
The GPIO interrupt allows the controller to wake-up periodically and poll system components while maintaining a very low average
power consumption. To achieve the lowest possible current during suspend mode, all I/O should be held at V
applies to internal port pins that may not be bonded in a particular package.
Typical code for entering suspend is shown below:
9.0
...
...
mov a, 09h
iowr FFh
nop
...
Suspend Mode
General-purpose I/O (GPIO) Ports
(Latch is Transparent
except in HAPI mode)
; All GPIO set to low-power state (no floating pins)
; Enable GPIO interrupts if desired for wake-up
; Set suspend and run bits
; Write to Status and Control Register – Enter suspend, wait for USB activity (or GPIO Interrupt)
; This executes before any ISR
; Remaining code for exiting suspend routine.
Interrupt
Enable
Interrupt
Controller
OE
Port Write
Reg_Bit
Port Read
Internal
Data Bus
STRB
GPIO
CFG
Data
In
Latch
Data
Interrupt
Latch
Data
Out
Latch
Figure 9-1. Block Diagram of a GPIO Pin
mode
2-bits
Q3*
Q1
14 k
V
CC
Q2
GPIO
PIN
*Port 0,1,2: Low I
Port 3: High I
CY7C66013C
CY7C66113C
sink
CC
sink
or Gnd. This also
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