NBC12430_06 ONSEMI [ON Semiconductor], NBC12430_06 Datasheet
NBC12430_06
Related parts for NBC12430_06
NBC12430_06 Summary of contents
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NBC12430, NBC12430A 3.3V/5V Programmable PLL Synthesized Clock Generator 50 MHz to 800 MHz The NBC12430 and NBC12430A are general purpose, PLL based synthesized clock sources. The VCO will operate over a frequency range of 400 MHz to 800 MHz. The ...
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MHz F with 16 MHz Crystal XTAL_SEL 2 FREF_EXT 9−BIT XTAL1 COUNTER 10−20MHz OSC 5 XTAL2 S_LOAD 7 P_LOAD 27 S_DATA 26 S_CLOCK Table 1. Output Division N [1:0] Output ...
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S_CLOCK S_DATA S_LOAD PLL_V CC FREF_EXT XTAL_SEL XTAL1 S_CLOCK 1 S_DATA 2 S_LOAD 3 PLL_V 4 CC PLL_V 5 CC FREF_EXT 6 XTAL_SEL 7 XTAL1 Figure 3. 32−Lead QFN ...
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The following gives a brief description of the functionality of the NBC12430 and NBC12430A Inputs and Outputs. Unless explicitly stated, all inputs are CMOS/TTL compatible with either pullup or pulldown resistors. The PECL outputs are capable of driving two series ...
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ATTRIBUTES Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Moisture Sensitivity (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. MAXIMUM RATINGS Symbol Parameter ...
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DC CHARACTERISTICS (V = 3.3 V ± 5 Symbol V Input HIGH Voltage IH LVCMOS/ LVTTL V Input LOW Voltage IL LVCMOS/ LVTTL I Input Current IN V Output HIGH Voltage OH PECL V Output LOW Voltage OL ...
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AC CHARACTERISTICS (V = 3.135 V to 5.25 V ± 5 Symbol Characteristic F Maximum Input Frequency MAXI F Maximum Output Frequency MAXO t Maximum PLL Lock Time LOCK t Period Jitter (RMS) jitter(pd) t Cycle−to−Cycle Jitter (Peak−to−Peak) ...
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The internal oscillator uses the external quartz crystal as the basis of its frequency reference. The output of the reference oscillator is divided by 16 before being sent to the phase detector. With a 16 MHz crystal, this provides a ...
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Programming the NBC12430 and NBC12430A is accomplished by properly configuring the internal dividers to produce the desired frequency at the outputs. The output frequency can by represented by this formula: F OUT + ((F XTAL or F REF_EXT ) B ...
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Table 5. Frequency Operating Range Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á VCO Frequency (MHz) Range for a Crystal Frequency (MHz) of: Á ...
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Most of the signals available on the TEST output pin are useful only for performance verification of the device itself. However, the PLL bypass mode may be of interest at the board level for functional debug. When T[2:0] is set ...
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Using the On−Board Crystal Oscillator The NBC12430 and NBC12430A feature a fully integrated on−board crystal oscillator to minimize system implementation costs. The oscillator is a series resonant, multivibrator type design as opposed to the more common parallel resonant oscillator design. ...
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A higher level of attenuation can be achieved by replacing the resistor with an appropriate valued inductor. Figure 8 shows a 1000 mH choke. This value choke will show a significant impedance at 10 KHz frequencies and above. Because of ...
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There are different ways to measure jitter and often they are confused with one another. The typical method of measuring jitter is to look at the timing signal with an oscilloscope and observe the variations in period−to−period or cycle−to−cycle. If ...
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S_DATA S_CLOCK t SETUP Figure 14. Setup and Hold S_DATA t S_LOAD SETUP Figure 15. Setup and Hold M[8:0] N[1:0] P_ LOAD t SETUP Figure 16. Setup and Hold F OUT F OUT Pulse Width Figure 17. Output Duty Cycle ...
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Driver Device Figure 18. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 − Termination of ECL Logic Devices.) ORDERING INFORMATION Device NBC12430FA NBC12430FAG NBC12430FAR2 NBC12430FAR2G NBC12430FN NBC12430FNG NBC12430FNR2 NBC12430FNR2G NBC12430AFA NBC12430AFAG NBC12430AFAR2 NBC12430AFAR2G NBC12430AFN NBC12430AFNG NBC12430AFNR2 ...
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Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ...
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0.010 (0.250) T L− NOTES: 1. DATUMS −L−, −M−, AND −N− DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT ...
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−T− DETAIL −Z− −AB− SEATING −AC− PLANE 0.10 (0.004) AC NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE ...
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D É É PIN ONE LOCATION É É 0.15 C TOP VIEW 2 X 0. 0.08 C SIDE VIEW 0. ...