NBC12430_06 ONSEMI [ON Semiconductor], NBC12430_06 Datasheet - Page 13

• Manufacturer Part Number: NBC12430_06
• Description: 3.3V/5V Programmable PLL Synthesized Clock Generator
• Manufacturer: ONSEMI [ON Semiconductor]

the resistor with an appropriate valued inductor. Figure 8
shows a 1000 mH choke. This value choke will show a
significant impedance at 10 KHz frequencies and above.
Because of the current draw and the voltage that must be
maintained on the PLL_V
inductor is required (less than 15 W). Generally, the
resistor/capacitor filter will be cheaper, easier to implement,
and provide an adequate level of supply filtering.
sub−nanosecond output edge rates and therefore a good
power supply bypassing scheme is a must. Figure 9 shows
a representative board layout for the NBC12430 and
NBC12430A . There exists many different potential board
layouts and the one pictured is but one. The important aspect
of the layout in Figure 9 is the low impedance connections
between V
Combining good quality general purpose chip capacitors
with good PCB layout techniques will produce effective
capacitor resonances at frequencies adequate to supply the
instantaneous switching current for the device outputs. It is
imperative that low inductance chip capacitors are used. It
is equally important that the board layout not introduce any
of the inductance saved by using the leadless capacitors.
Thin interconnect traces between the capacitor and the
power plane should be avoided and multiple large vias
should be used to tie the capacitors to the buried power
planes. Fat interconnect and large vias will help to minimize
layout induced inductance and thus maximize the series
resonant point of the bypass capacitors.
É É É É
A higher level of attenuation can be achieved by replacing
The
R1
XTAL
Figure 9. PCB Board Layout (PLCC−28)
C3
NBC12430
CC
and GND for the bypass capacitors.
C2
C1
É É É
É É É
É É É
É É É
1
and
CC
pin, a low DC resistance
NBC12430A
É É É
É É É
É É É
É É É
R1 = 10−15 W
C1 = 0.01 mF
C2 = 22 mF
C3 = 0.1 mF
É É É É
É É
C1
= V
= GND
= Via
provide
CC
http://onsemi.com
13
connection to the device. The oscillator is a series resonant
circuit and the voltage amplitude across the crystal is
relatively small. It is imperative that no actively switching
signals cross under the crystal as crosstalk energy coupled
to these lines could significantly impact the jitter of the
device. Special attention should be paid to the layout of the
crystal to ensure a stable, jitter free interface between the
crystal and the on−board oscillator. Note the provisions for
placing a resistor across the crystal oscillator terminals as
discussed in the crystal oscillator section of this data sheet.
design features to minimize the susceptibility to power
supply noise (isolated power and grounds and fully
differential PLL), there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter and bypass schemes
discussed in this section should be adequate to eliminate
power supply noise−related problems in most designs.
Jitter Performance
generation and distribution. Clock jitter can be defined as the
deviation in a clock’s output transition from its ideal
position.
variation between two adjacent cycles over a defined
number of observed cycles. The number of cycles observed
is application dependent but the JEDEC specification is
1000 cycles.
highest and lowest acquired value and is represented as the
width of the Gaussian base.
Note the dotted lines circling the crystal oscillator
Although the NBC12430 and NBC12430A have several
Jitter is a common parameter associated with clock
Cycle−to−Cycle Jitter (short−term) is the period
Peak−to−Peak Jitter is the difference between the
Figure 10. Cycle−to−Cycle Jitter
Figure 11. Peak−to−Peak Jitter
T
0
Time
T
JITTER(cycle−cycle)
= T
T
1
1
− T
Typical
Gaussian
Distribution
0
RMS
or one
Sigma
Jitter