PCF8523 NXP [NXP Semiconductors], PCF8523 Datasheet - Page 37

• Manufacturer Part Number: PCF8523
• Description: Real-Time Clock (RTC) and calendar
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCF8523
Product data sheet
8.9.4 Second interrupt timer
If a new value of n is written before the end of the actual timer-period, this value will take
immediate effect. It is not recommended to change n without first disabling the counter by
setting TBC logic 0 (register Tmr_CLKOUT_ctrl). The update of n is asynchronous to the
timer clock. Therefore changing it on the fly could result in a corrupted value loaded into
the countdown counter. This can result in an undetermined countdown period for the first
period. The countdown value n will be correctly stored and correctly loaded on
subsequent timer-periods.
Loading the counter with 0 effectively stops the timer.
When starting the countdown timer for the first time, only the first period will not have a
fixed duration. The amount of inaccuracy for the first timer-period depends on the chosen
source clock; see
When the interrupt generation is enabled (CTBIE = 1) and the countdown timer flag CTAF
is set logic 1 interrupt signals on INT1 and INT2 are generated. The interrupt may be
generated as a pulsed signal every countdown period or as a permanently active signal,
which follows the condition of CTBF (register Control_2). The TBM bit (register
Tmr_CLKOUT_ctrl) is used to control this mode selection. Interrupt output may be
disabled with the CTBIE bit (register Control_2).
PCF8523 has a pre-defined timer, which is used to generate an interrupt once per second.
The pulse generator for the second interrupt timer operates from an internal 64 Hz clock
and generates a pulse of
timer and can be switched on and off by the SIE bit in register Control_1 (00h).
The interrupt generated by the second interrupt timer may be generated as pulsed signal
every second or as a permanent active signal. The TAM bit (register Tmr_CLKOUT_ctrl) is
used to control the interrupt generation mode.
When the second interrupt timer is enabled (SIE = 1), then the timer sets the flag SF
(register Control_2) every second (see
interface. Instructions, how to clear a flag, is given in
Table 40.
When SF is logic 1:
SIE
0
1
•
•
If TAM (register Tmr_CLKOUT_ctrl) is logic 1 the interrupt is generated as a pulsed
signal every second.
If TAM is logic 0, the interrupt is a permanently active signal that remains, until SF is
cleared.
Effect of bit SIE on INT1 and bit SF
All information provided in this document is subject to legal disclaimers.
Result on INT1
no interrupt generated
an interrupt once per second
Table
Rev. 3 — 30 March 2011
39.
1

64
s in duration. It is independent of the watchdog or countdown
Table
40). SF may only be cleared by using the
Result on SF
SF never set
SF set when seconds counter increments
Real-Time Clock (RTC) and calendar
Section
8.7.5.
PCF8523
© NXP B.V. 2011. All rights reserved.
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