PCF8523 NXP [NXP Semiconductors], PCF8523 Datasheet - Page 39
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PCF8523
Manufacturer Part Number
PCF8523
Description
Real-Time Clock (RTC) and calendar
Manufacturer
NXP [NXP Semiconductors]
Datasheet
1.PCF8523.pdf
(66 pages)
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NXP Semiconductors
PCF8523
Product data sheet
Table 42.
Pulse mode, bit TBM set logic 1.
[1]
[2]
When flags like SF, CTAF, WTAF, and CTBF are cleared before the end of the interrupt
pulse, then the interrupt pulse is shortened. This allows the source of a system interrupt to
be cleared immediately when it is serviced, i.e. the system does not have to wait for the
completion of the pulse before continuing; see
clearing flags can be found in
found in
Source clock (Hz).
4096
64
1
1
1
Fig 23. Example of shortening the INT1 pulse by clearing the SF flag
60
3600
n = loaded timer register value. Timer stops when n = 0.
If pulse period is shorter than the setting via bit TBW, the interrupt pulse width is set to 15.625 ms.
(1) Indicates normal duration of INT1 pulse.
Section
The timing shown for clearing bit SF is also valid for the non-pulsed interrupt mode, i.e. when
TAM set logic 0, where the INT1 pulse may be shortened by setting SIE logic 0.
Interrupt low pulse width for timer B
seconds counter
All information provided in this document is subject to legal disclaimers.
8.9.2.1.
instruction
INT1
SCL
Rev. 3 — 30 March 2011
SF
58
Section
Interrupt pulse width
n = 1
122 s
7.812 ms
see
:
:
Table 36
59
[1]
8.7.5. Instructions for clearing the bit WTAF can be
CLEAR INSTRUCTION
Figure 23
Real-Time Clock (RTC) and calendar
and
n > 1
244 s
see
:
:
:
Figure
Table 36
[1]
24. Instructions for
013aaa333
PCF8523
© NXP B.V. 2011. All rights reserved.
[2]
(1)
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