UDA1343 PHILIPS [NXP Semiconductors], UDA1343 Datasheet
UDA1343
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UDA1343 Summary of contents
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... DATA SHEET UDA1343TT Economy audio CODEC with features Preliminary specification File under Integrated Circuits, IC01 INTEGRATED CIRCUITS 2000 Jan 12 ...
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... The UDA1343TT is equipped with a digital mixer for mixing the ADC signal directly to the playback signal (for example for Karaoke applications). In the mixing mode the ADC output signal can be output before or after the mixer ...
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... A-weighted 44.1 kHz kHz 44.1 kHz kHz dB; A-weighted f = 44.1 kHz kHz s code = 0; A-weighted f = 44.1 kHz kHz s 3 Preliminary specification UDA1343TT TYP. MAX. UNIT 3.0 3.6 V 3.0 3.6 V 3.0 3 100 2.5 mA 200 300 A +85 C 1.0 V ...
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... The input voltage to the ADC scales proportionally with the power supply. 3. The performance figures and input voltage of the ADC are given with the PGA gain set to 0 dB. 2000 Jan 12 CONDITIONS MIN. 4 Preliminary specification UDA1343TT TYP. MAX. UNIT ...
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... ADC ADC DECIMATION FILTER DC/VOLUME/MUTE DIGITAL INTERFACE DE-EMPHASIS/VOLUME/MUTE DIGITAL MIXER INTERPOLATION FILTER NOISE SHAPER DAC DAC DDO V SSO V DDA(DAC) Fig.1 Block diagram. 5 Preliminary specification UDA1343TT V ADCN V ref( VINR PGA 8 TEST1 21 TEST2 20 RESET 13 L3MODE 14 L3-BUS L3CLOCK INTERFACE 15 L3DATA ...
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... SSO V 28 analog pad ref(D) 2000 Jan 12 TYPE 6 Preliminary specification UDA1343TT DESCRIPTION ADC analog ground ADC analog supply voltage ADC input left ADC reference voltage ADC input right ADC negative reference voltage ADC positive reference voltage test pin 1 ...
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... SYSCLK clock 21 TEST2 cycles to properly reset the device. 20 RESET Analog-to-Digital Converter (ADC) DATAI 19 The stereo ADC of the UDA1343TT consists of two DATAO 18 5th-order Sigma-Delta modulators. They have a modified WS 17 Ritchie-coder architecture in a differential switched capacitor implementation. The oversampling ratio is 64. BCK ...
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... Dynamic range 0 0.45f Gain DC 2000 Jan 12 Digital silence detector The UDA1343 is equipped with a digital silence detector on the digital data input. This detects whether a certain sin x ----------- - characteristic. amount of consecutive samples are 0. The status of the x digital silence detector can be read from the microcontroller interface ...
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... Philips Semiconductors Economy audio CODEC with features Digital mixer The UDA1343TT has a digital mixer which can mix the ADC signal to the playback signal. A functional block diagram of the mixer mode is given in Fig.4. When the device is in mixer mode, care is taken to avoid clipping. This is done by reducing both signals before mixing ...
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... Philips Semiconductors Economy audio CODEC with features Digital output signal The output to the digital output of the UDA1343TT can be selected from 3 positions, using the two bits ADC_OUT select in the L3 microcontroller interface. The 3 positions are as follows: Directly from the ADC and decimator (default) ...
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Acrobat reader. white to force landscape pages to be ... WS LEFT BCK DATA MSB B2 MSB INPUT ...
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... Philips Semiconductors Economy audio CODEC with features L3 INTERFACE Introduction The UDA1343TT has a microcontroller input mode. In the microcontroller mode, all the digital sound processing features and the system controlling features can be controlled by the microcontroller. The controllable features are: System clock frequency Data input format ...
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... The device writes the data from the requested register to the bus (two bytes). t CLK(L3)L t CLK(L3)H t su(L3)A t su(L3)DA t h(L3)DA BIT 0 Fig.6 Timing address mode. 13 Preliminary specification UDA1343TT t su(L3)A t h(L3)A T cy(CLK)(L3) BIT 7 MGL723 ...
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... Economy audio CODEC with features handbook, full pagewidth t stp(L3) L3MODE t su(L3)D L3CLOCK L3DATA write L3DATA read t en(L3)DA 2000 Jan 12 t CLK(L3)L T cy(CLK)L3 t CLK(L3)H t h(L3)DA t su(L3)DA BIT 0 t h(L3)R t su(L3)R Fig.7 Data write and read mode timing. 14 Preliminary specification UDA1343TT t stp(L3) t h(L3)D t h(L3)DA BIT 7 t dis(L3)DA MGL889 ...
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Acrobat reader. white to force landscape pages to be ... L3 wake-up pulse after power-up L3CLOCK L3MODE device address 0 1 L3DATA DOM bits ...
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... A6 A5 FIRST IN TIME BIT 0 BIT 1 BIT 2 BIT valid invalid D15 S14 D13 D12 Preliminary specification UDA1343TT LATEST IN TIME BIT 4 BIT 5 BIT D11 D10 LATEST IN TIME BIT 4 BIT 5 BIT 6 ...
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Acrobat reader. white to force landscape pages to be ... L3 settings L3 REGISTER MAPPING Table 8 L3 register mapping including default register settings; ...
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Acrobat reader. white to force landscape pages to be ... Table 9 L3 register mapping including default register settings; bits REG ...
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... MSB justified output/ LSB-justified 24 bits input 0 1 LSB justified, 24 bits : : other codes are reserved for future use FUNCTION mixer disabled mixer enabled 19 Preliminary specification UDA1343TT PON DAC 0 DAC powered down 1 DAC powered up SC1 SC0 ...
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... S ILENCE DETECTOR ENABLE SETTING A 1-bit value to enable or disable the digital silence detection signal. Table 19 Silence detector control setting FUNCTION 3200 samples 4800 samples 9600 samples 19600 samples 20 Preliminary specification UDA1343TT FUNCTION VOLUME (dB 0.25 0.5 0. ...
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... Table 22 Mixer mute D IGITAL DE FUNCTION A 2-bit value to enable the digital de-emphasis filter. no muting muting Table 23 De-emphasis settings DE2 A 1-bit value to enable the digital DC filter (see Table 24). 21 Preliminary specification UDA1343TT dB in steps of 0.25 dB (see Table 20). VC-AD2 VC-AD1 VC-AD0 VC-IIS2 VC-IIS1 VC-IIS0 ...
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... ADC channels enabled, bias block turned on PGAL1, PGAR1 Preliminary specification UDA1343TT FUNCTION FUNCTION PGAL0, PGAR0 FUNCTION gain gain gain gain gain gain gain gain gain : ...
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... S-bus left channel is digitally zero 2 S-bus right channel is digitally zero 2 S-bus input channel = 25 C; unless otherwise specified. CONDITIONS note 1 human body model; note 2 machine model; note 2 PARAMETER 23 Preliminary specification UDA1343TT MIN. MAX. 5.0 150 65 +125 40 +85 CONDITIONS VALUE in free air 110 ...
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... ADC power-down operating mode DAC power-down operating mode DAC power-down operating mode ADC and DAC power-down referenced to V SSA(ADC kHz i referenced to V SSA(DAC) 24 Preliminary specification UDA1343TT MIN. TYP. MAX. 2.4 3.0 3.6 2.4 3.0 3.6 2.4 3.0 3.6 10 100 2.5 200 5 300 2.0 5.0 0.5 0.8 1 ...
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... ripple(p- setting 3 dB setting 6 dB setting 9 dB setting 12 dB setting 15 dB setting 18 dB setting 21 dB setting 24 dB setting 25 Preliminary specification UDA1343TT MIN. TYP. MAX. 3.5 3 200 = all voltages referenced to ground; L MIN. TYP. MAX. 1.0 0 ...
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... A-weighted f = 44.1 kHz kHz s code = 0; A-weighted f = 44.1 kHz kHz s A-weighted; digital silence kHz; ripple ripple(p-p) 26 Preliminary specification UDA1343TT TYP. MAX. UNIT 85 dB tbf dB tbf dB tbf dB tbf dB tbf dB tbf dB tbf dB tbf tbf dB tbf dB tbf ...
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... MHz sys f 19.2 MHz sys address mode address mode data transfer mode data transfer mode data transfer mode and address mode data transfer mode and address mode 27 Preliminary specification UDA1343TT MIN. TYP. MAX 781 520 390 ns 0.30T ...
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... WS t BCKH t r BCK T cy DATAO DATAI 2000 Jan 12 = 44.1 kHz typical 44.1 kHz typical CWL T sys Fig.10 System clock timing. t s(WS) t h(WS BCKL t d(DATAO-WS) Fig.11 Serial interface timing. 28 Preliminary specification UDA1343TT MGR984 t d(DATAO-BCK) t h(DATAO) t s(DATAI) t h(DATAI) MGL885 ...
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... RESET L3DATA SSO V DDO C26 100 nF ( 100 F R25 ( DDO Fig.12 Application diagram. 29 Preliminary specification UDA1343TT V DDD R28 1 V ADCP V SSD V DDD ref(A) 4 C22 100 nF ( VOUTL R22 ( ...
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... 2.5 scale (1) ( 0.30 0.2 9.8 4.5 6.6 0.65 0.19 0.1 9.6 4.3 6.2 REFERENCES JEDEC EIAJ MO-153 30 Preliminary specification detail 0.75 0.4 1.0 0.2 0.13 0.50 0.3 EUROPEAN PROJECTION UDA1343TT SOT361 ( 0.8 8 0.1 o 0.5 0 ISSUE DATE 95-02-04 99-12-27 ...
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... Use a low voltage ( less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds 300 C. When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 C. 31 Preliminary specification UDA1343TT ...
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... Philips for any damages resulting from such improper use or sale. 2000 Jan 12 SOLDERING METHOD WAVE not suitable (2) not suitable suitable (3)(4) not recommended (5) not recommended 32 Preliminary specification UDA1343TT (1) REFLOW suitable suitable suitable suitable suitable ...
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... Philips Semiconductors Economy audio CODEC with features 2000 Jan 12 NOTES 33 Preliminary specification UDA1343TT ...
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... Philips Semiconductors Economy audio CODEC with features 2000 Jan 12 NOTES 34 Preliminary specification UDA1343TT ...
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... Philips Semiconductors Economy audio CODEC with features 2000 Jan 12 NOTES 35 Preliminary specification UDA1343TT ...
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Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. + 101 ...