UDA1343 PHILIPS [NXP Semiconductors], UDA1343 Datasheet - Page 12

• Manufacturer Part Number: UDA1343
• Description: Economy audio CODEC with features
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
L3 INTERFACE
Introduction
The UDA1343TT has a microcontroller input mode. In the
microcontroller mode, all the digital sound processing
features and the system controlling features can be
controlled by the microcontroller. The controllable features
are:
The exchange of data and control information between the
microcontroller and the UDA1343TT is accomplished
through a serial hardware interface comprising the
following pins:
Information transfer via the microcontroller bus is
organized LSB first, and in accordance with the so called
‘L3’ format, in which two different modes of operation can
be distinguished; address mode and data transfer mode
(see Fig 6).
Important: when the device is powered-up, at least one
L3CLOCK pulse must be sent to the L3 interface to
wake-up the interface prior to sending to the device. This
is only needed once after the device is powered-up.
Device addressing
The device addressing mode is used to select a device for
subsequent data transfer. The address mode is
characterized by L3MODE being LOW and a burst of
8 pulses on L3CLOCK, accompanied by 8 bits.
The fundamental timing is illustrated in Fig.6.
2000 Jan 12
System clock frequency
Data input format
Power control
DC filtering
De-emphasis
Volume: master volume, I
volume
Mute: master mute, I
Mixer settings
PGA gain settings
Digital silence control settings
Polarity settings of the ADC and the DAC.
L3DATA: microcontroller interface data line
L3MODE: microcontroller interface mode line
L3CLOCK: microcontroller interface clock line.
Economy audio CODEC with features
2
S-bus mute and ADC mute
2
S-bus mixer volume and ADC
12
Basically, 2 types of transfer can be defined; data transfer
to the device and data transfer from the device; see
Table 4.
Table 4 Selection of data transfer
As can be seen in Table 4, the DATA and STATUS read
and write actions are combined.
The device address consists of one byte, which is split up
into two parts:
As can be seen in Table 4, there are two types of data
transfers, being DATA and STATUS which can be read
and written.
Register addressing
After sending the device address, including the flags (the
DOM bits) whether the information is read or written, one
byte is sent with the destination register address using
7 bits, and 1 bit which signals whether information will be
read or written. The fundamental timing for the data mode
is illustrated in Fig.7.
Basically there are 3 cases for register addressing:
1. Register addressing for L3 write: the first bit is at
2. Prepare read addressing: the first bit of the byte is at
3. The read action itself: in this case the device returns a
BIT 1
DOM
Bits 7 to 2 represent a 6-bit device address
Bits 1 and 0 represent the type of data transfer
according to Table 4.
0
0
1
1
logic 0 indicating a write action to the destination
register, and is followed by 7 register address bits.
logic 1, signalling data will be read from the register
indicated.
register address prior to sending data from that
register. When the first bit of the byte is at logic 0, the
register address is valid, if the first bit is at logic 1 the
register address is invalid.
BIT 0
DOM
0
1
0
1
not used
not used
DATA and STATUS write or pre-read
DATA and STATUS read
TRANSFER
Preliminary specification
UDA1343TT