DAC1401D125HL NXP [NXP Semiconductors], DAC1401D125HL Datasheet - Page 14

• Manufacturer Part Number: DAC1401D125HL
• Description: Dual 14-bit DAC, up to 125 Msps
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
10. Application information
DAC1401D125_1
Product data sheet
10.1 General description
10.2 Input data
The DAC1401D125 is a dual 14-bit DAC operating up to 125 Msps. Each DAC consists of
a segmented architecture, comprising a 7-bit thermometer sub-DAC and a 7-bit binary
weighted sub-DAC.
Two modes are available for the digital input depending on the status of the pin MODE. In
Dual port mode, each DAC uses its own data input line at the same frequency as the
update rate. In Interleaved mode, both DACs use the same data input line at twice the
update rate.
Each DAC generates on pins IOUTAP/IOUTAN and IOUTBP/IOUTBN two complementary
current outputs. This provides a full-scale output current (I
common or two independent full-scale current controls can be selected for both channels
using pin GAINCTRL. An internal reference is available for the reference current which is
externally adjustable using pin REFIO.
The DAC1401D125 operates at 3.3 V and has separate digital and analog power supplies.
Pin PWD is used to power-down the device. The digital input is 1.8 V compliant, 3.3 V
compliant and 5 V tolerant.
The DAC1401D125 input follows a straight binary coding where DA13 and DB13 are the
Most Significant Bits (MSB) and DA0 and DB0 are the Least Significant Bits (LSB).
The setting applied to pin MODE defines whether the DAC1401D125 operates in Dual
port mode or in Interleaved mode (see
Fig 13. Analog supply current as a function of the output current
(mA)
I
DDA
60
40
20
0
0
Rev. 01 — 13 November 2008
5
Table
10
6).
Dual 14-bit DAC, up to 125 Msps
O(fs)
DAC1401D125
15
), up to 20 mA. A single
l
O
(mA)
001aaj032
© NXP B.V. 2008. All rights reserved.
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