DAC1401D125HL NXP [NXP Semiconductors], DAC1401D125HL Datasheet - Page 16

• Manufacturer Part Number: DAC1401D125HL
• Description: Dual 14-bit DAC, up to 125 Msps
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
DAC1401D125_1
Product data sheet
In Interleaved mode, both DACs use the same data and clock inputs at twice the update
rate. Data enters the latch on the rising edge of IQWRT. The data is sent to either latch A
or latch B, depending on the value of IQSEL. The IQSEL transition must occur when
IQWRT and IQCLK are LOW.
The IQCLK is divided by 2 internally and the data is transferred to the DAC latch. It is
updated on its rising edge. When IQRESET is HIGH, IQCLK is disabled, see
Fig 16. Interleaved mode
Fig 17. Interleaved mode timing
IOUTBP, IOUTBN
IOUTAP, IOUTAN
DA13 to DA0/
DB13 to DB0
IQRESET
IQWRT
IQCLK
IQSEL
DA13 to DA0
Rev. 01 — 13 November 2008
IQRESET
IQWRT
IQSEL
IQCLK
XX
XX
N
N+1
N+2
14
14
N+3
INPUT A
INPUT B
N+1
LATCH
LATCH
N
2
N+4
Dual 14-bit DAC, up to 125 Msps
14
14
N+5
N+2
N+3
DAC1401D125
LATCH
LATCH
DAC A
DAC B
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N+6
N+4
N+5
N+7
© NXP B.V. 2008. All rights reserved.
001aai940
Figure
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17.