DAC1405D750HW NXP [NXP Semiconductors], DAC1405D750HW Datasheet - Page 31

• Manufacturer Part Number: DAC1405D750HW
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
DAC1405D750_1
Preliminary data sheet
10.12 Analog output
Table 41.
Default settings are shown highlighted.
The DAC1405D750 has two output channels each of which produces two complementary
current outputs. These allow the even-order harmonics and noise to be reduced. The pins
are IOUTAP/IOUTAN and IOUTBP/IOUTBN, respectively and need to be connected via a
load resistor R
Refer to
of a parallel combination of NMOS current sources, and their associated switches, for
each segment.
The cascode source configuration increases the output impedance of the source, thus
improving the dynamic performance of the DAC by introducing less distortion.
The device can provide an output level of up to 2 V
following stages and the targeted performances.
DAC_OFFSET[11:0]
Decimal
−2048
−2047
...
−1
0
+1
...
+2046
+2047
Fig 12. Equivalent analog output circuit (one DAC)
Figure 12
Digital offset adjustment
L
All information provided in this document is subject to legal disclaimers.
to the 3.3 V analog power supply (V
for the equivalent analog output circuit of one DAC. This circuit consists
Rev. 01 — 10 March 2010
AGND
Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
Two’s complement
1000 0000 0000
1000 0000 0001
...
1111 1111 1111
0000 0000 0000
0000 0000 0001
...
0111 1111 1110
0111 1111 1111
AGND
IOUTAP/IOUTBP
IOUTAN/IOUTBN
o(p-p)
DDA(3V3)
depending on the application, the
DAC1405D750
).
Offset applied
−4096
−4094
...
−2
0
+2
...
+4092
+4094
V
DDA(3V3)
R L
001aah019
R L
© NXP B.V. 2010. All rights reserved.
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