DAC1405D750HW NXP [NXP Semiconductors], DAC1405D750HW Datasheet - Page 42

• Manufacturer Part Number: DAC1405D750HW
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
17. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. COMMon register (address 00h)
Table 11. TXCFG register (address 01h)
Table 12. PLLCFG register (address 02h)
Table 13. FREQNCO_LSB register (address 03h) bit
Table 14. FREQNCO_LISB register (address 04h) bit
Table 15. FREQNCO_UISB register (address 05h) bit
Table 16. FREQNCO_MSB register (address 06h) bit
Table 17. PHINCO_LSB register (address 07h) bit
Table 18. PHINCO_MSB register (address 08h) bit
Table 19. DAC_A_Cfg_1 register (address 09h) bit
Table 20. DAC_A_Cfg_2 register (address 0Ah) bit
Table 21. DAC_A_Cfg_3 register (address 0Bh) bit
18. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10. Input timing diagram when internal PLL
Fig 11. Internal reference configuration . . . . . . . . . . . . . .29
Fig 12. Equivalent analog output circuit (one DAC) . . . . .31
Fig 13. 1 V
Fig 14. 2 V
Fig 15. An example of a DC interface to a 1.7 V
Fig 16. An example of a DC interface to a 3.3 V
DAC1405D750_1
Preliminary data sheet
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . .4
SPI timing diagram . . . . . . . . . . . . . . . . . . . . . . .14
Dual-port mode . . . . . . . . . . . . . . . . . . . . . . . . . .22
Interleaved mode operation . . . . . . . . . . . . . . . . .23
Interleaved mode timing (8x interpolation,
latch on rising edge) . . . . . . . . . . . . . . . . . . . . . .23
LVDS clock configuration . . . . . . . . . . . . . . . . . . .24
Interfacing CML to LVDS . . . . . . . . . . . . . . . . . . .24
bypassed (off) . . . . . . . . . . . . . . . . . . . . . . . . . . .25
AQM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
SPI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Read or Write mode access description . . . . .14
bit description . . . . . . . . . . . . . . . . . . . . . . . . .17
bit description . . . . . . . . . . . . . . . . . . . . . . . . .17
bit description . . . . . . . . . . . . . . . . . . . . . . . . .18
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Ordering information . . . . . . . . . . . . . . . . . . . . .2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . .8
Thermal characteristics . . . . . . . . . . . . . . . . . . .8
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .9
Number of bytes transferred . . . . . . . . . . . . . .14
SPI timing characteristics . . . . . . . . . . . . . . . .15
Register allocation map . . . . . . . . . . . . . . . . . .16
o(p-p)
o(p-p)
differential output with transformer . . . . .32
differential output with transformer . . . . .33
All information provided in this document is subject to legal disclaimers.
I(cm)
I(cm)
Rev. 01 — 10 March 2010
Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
Table 22. DAC_B_Cfg_1 register (address 0Ch) bit
Table 23. DAC_B_Cfg_2 register (address 0Dh) bit
Table 24. DAC_B_Cfg_3 register (address 0Eh) bit
Table 25. DAC_Cfg register (address 0Fh)
Table 26. SYNC_Cfg register (address 10h)
Table 27. DAC_A_Aux_MSB register (address 1Ah)
Table 28. DAC_A_Aux_LSB register (address 1Bh)
Table 29. DAC_B_Aux_MSB register (address 1Ch)
Table 30. DAC_B_Aux_LSB register (address 1Dh)
Table 31. Recommended configuration . . . . . . . . . . . . . . 22
Table 32. Mode selection . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 33. Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 34. Sample clock phase and polarity examples . . 25
Table 35. Optimum external PLL timing settings . . . . . . 25
Table 36. Interpolation filter coefficients . . . . . . . . . . . . . 26
Table 37. Inversion filter coefficients . . . . . . . . . . . . . . . . 27
Table 38. DAC transfer function . . . . . . . . . . . . . . . . . . . 28
Table 39. I
Table 40. I
Table 41. Digital offset adjustment . . . . . . . . . . . . . . . . . 31
Table 42. Auxiliary DAC transfer function . . . . . . . . . . . . 32
Table 43. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 44. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 39
Fig 17. An example of a DC interface to a 1.7 V
Fig 18. An example of a DC interface to a 3.3 V
Fig 19. An example of an AC interface to a 0.5 V
Fig 20. Package outline SOT638-1 (HTQFP100) . . . . . . 37
AQM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
AQM using auxiliary DACs . . . . . . . . . . . . . . . . . 34
AQM using auxiliary DACs . . . . . . . . . . . . . . . . . 35
AQM using auxiliary DACs . . . . . . . . . . . . . . . . . 36
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 20
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 21
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 21
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 21
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 21
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 21
O(fs)
O(fs)
coarse adjustment . . . . . . . . . . . . . . . . . . 29
fine adjustment . . . . . . . . . . . . . . . . . . . . 30
DAC1405D750
© NXP B.V. 2010. All rights reserved.
I(cm)
I(cm)
I(cm)
42 of 43