DSP56100 MOTOROLA [Motorola, Inc], DSP56100 Datasheet - Page 44

• Manufacturer Part Number: DSP56100
• Description: 16-bit General Purpose Digital Signal Processor
• Manufacturer: MOTOROLA [Motorola, Inc]

Careful synchronization is required when reading multibit registers that are written by another asynchronous
system. This is a common problem when two asynchronous systems are connected. The situation exists in
the Host port. The considerations for proper operation are discussed below.
Host Programmer Considerations
1. Unsynchronized Reading of Receive Byte Registers
2. Overwriting Transmit Byte Registers
3. Synchronization of Status Bits from DSP to Host
4. Overwriting the Host Vector
5. Cancelling a Pending Host Command Exception
DSP Programmer Considerations
1. Reading HF0 and HF1 as an Encoded Pair
MOTOROLA
When reading receive byte registers, RXH or RXL, the Host programmer should use interrupts or poll
the RXDF flag which indicates that data is available. This assures that the data in the receive byte
registers will be stable.
The Host programmer should not write to the transmit byte registers, TXH or TXL, unless the TXDE bit
is set indicating that the transmit byte registers are empty. This guarantees that the transmit byte
registers will transfer valid data to the HRX register.
HC, HREQ, DMA, HF3, HF2, TRDY, TXDE, and RXDF (refer to DSP56166 User’s Manual, I/O Interface
section, Host/DMA Interface Programming Model for descriptions of these status bits) status bits are
set or cleared from inside the DSP and read by the Host processor. The Host can read these status bits
very quickly without regard to the clock rate used by the DSP, but the possibility exists that the state of
the bit could be changing during the read operation. This is generally not a system problem, since the
bit will be read correctly in the next pass of any Host polling routine.
However, if the Host asserts the HEN for more than timing number 101 (T101), with a minimum cycle
time of timing number 103 (T103), then the status is guaranteed to be stable
A potential problem exists when reading status bits HF3 and HF2 as an encoded pair. If the DSP
changes HF3 and HF2 from 00 to 11, there is a small probability that the Host could read the bits during
the transition and receive 01 or 10 instead of 11. If the combination of HF3 and HF2 has significance,
the Host could read the wrong combination.
Solution:
a. Read the bits twice and check for consensus.
b. Assert HEN access for T101a so that status bit transitions are stabilized.
The Host programmer should change the Host Vector register only when the Host Command bit (HC)
is clear. This change will guarantee that the DSP interrupt control logic will receive a stable vector.
The Host processor may elect to clear the HC bit to cancel the Host Command Exception request at
any time before it is recognized by the DSP. Because the Host does not know exactly when the
exception will be recognized (due to exception processing synchronization and pipeline delays), the
DSP may execute the Host exception after the HC bit is cleared. For these reasons, the HV bits must
not be changed at the same time the HC bit is cleared.
DMA, HF1, HF0, and HCP, HTDE, and HRDF (refer to DSP56166User’s Manual, I/O Interface section,
Host/DMA Interface Programming Model for descriptions of these status bits) status bits are set or
cleared by the Host processor side of the interface. These bits are individually synchronized to the DSP
clock.
A potential problem exists when reading status bits HF1 and HF2 as an encoded pair, i.e., the four
combinations 00, 01, 10, and 11 each have significance. A very small probability exists that the DSP
will read the status bits synchronized during transition. The solution to this potential problem is to read
the bits twice for consensus.
HOST PORT USAGE CONSIDERATIONS
DSP56166 Technical Data Sheet
PRELIMINARY - 6/15/93
34