ADSP-2191 AD [Analog Devices], ADSP-2191 Datasheet
ADSP-2191
Available stocks
Related parts for ADSP-2191
ADSP-2191 Summary of contents
Page 1
... I/O DATA I/O REGISTERS (MEMORY-MAPPED) CONTROL ALU STATUS BUFFERS SYSTEM INTERRUPT CONTROLLER One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A. Tel:781/329-4700 Fax:781/326-8703 DSP Microcomputer ADSP-2191M DATA DATA DATA EMULATION DATA EXTERNAL PORT 18 ADDR BUS MUX DATA BUS MUX I/O PROCESSOR HOST PORT SERIAL PORTS ...
Page 2
... ADSP-2191M INTEGRATION FEATURES 160 K Bytes On-Chip RAM Configured as 32K Words 24-Bit Memory RAM and 32K Words 16-Bit Memory RAM Dual-Purpose 24-Bit Memory for Both Instruction and Data Storage Independent ALU, Multiplier/Accumulator, and Barrel Shifter Computational Units with Dual 40-bit Accumulators Unified Memory Space Allows Flexible Address Genera- ...
Page 3
... The ADSP-2191M is available in 144-lead LQFP and 144-ball mini-BGA packages. Fabricated in a high-speed, low-power, CMOS process, the ADSP-2191M operates with a 6.25 ns instruction cycle time (160 MIPS). All instructions, except single-word instructions, execute in one processor. The ADSP-2191M’s flexible architecture and comprehensive instruction set support multiple operations in parallel ...
Page 4
... The priority of each peripheral for interrupt service is determined by these assignments. There are three serial ports on the ADSP-2191M that provide a complete synchronous, full-duplex serial interface. This interface includes optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of opera- ...
Page 5
... A bit in each timer’s configuration register enables or disables the corresponding timer independently of the others. Memory Architecture The ADSP-2191M DSP provides 64K words of on-chip SRAM memory. This memory is divided into four 16K blocks located on memory Page 0 in the DSP’s memory map. In addition to the ...
Page 6
... Before a cross page jump or call, the program must set the program sequencer’s IJPG register to the appropriate memory page. The ADSP-2191M has 1K word of on-chip ROM that holds boot routines. If peripheral booting is selected, the DSP starts executing instructions from the on-chip boot ROM, which starts the boot process from the selected peripheral. tion, see “ ...
Page 7
... DSP’s state DMA Controller 7 7 The ADSP-2191M has a DMA controller that supports 8 8 automated data transfers with minimal overhead for the DSP 9 9 core. Cycle stealing DMA transfers can occur between the 10 10 ADSP-2191M’s internal memory and any of its DMA-capable ...
Page 8
... Memory DMA 11—Lowest Host Port The ADSP-2191M’s Host port functions as a slave on the external bus of an external Host. The Host port interface lets a Host read from or write to the DSP’s memory space, boot space, or internal I/O space. Examples of Hosts include external micro- controllers, microprocessors, or ASICs ...
Page 9
... Otherwise, the Host port interface asserts ACK when it has completed the memory access successfully. DSP Serial Ports (SPORTs) The ADSP-2191M incorporates three complete synchronous serial ports (SPORT0, SPORT1, and SPORT2) for serial and multiprocessor communications. The SPORTs support the following features: Bidirectional operation— ...
Page 10
... Power-Down Core Power-Down Core/Peripherals Power-Down All Idle Mode When the ADSP-2191M is in Idle mode, the DSP core stops executing instructions, retains the contents of the instruction pipeline, and waits for an interrupt. The core clock and peripheral clock continue running. To enter Idle mode, the DSP can execute the IDLE instruction anywhere in code ...
Page 11
... IDLE. Clock Signals The ADSP-2191M can be clocked by a crystal oscillator or a buffered, shaped clock derived from an external clock oscillator crystal oscillator is used, the crystal should be connected across the CLKIN and XTAL pins, with two capacitors and a ...
Page 12
... OPMODE bit appropriately during runtime prior to using the corresponding peripheral. Bus Request and Bus Grant The ADSP-2191M can relinquish control of the data and address buses to an external device. When the external device requires access to the bus, it asserts the bus request (BR) signal. The (BR) signal is arbitrated with core and peripheral requests ...
Page 13
... The bus request feature operates at all times, even while the DSP is booting and RESET is active. The ADSP-2191M asserts the BGH pin when it is ready to start another external port access, but is held off because the bus was previously granted. This mechanism can be extended to define more complex arbitration protocols for implementing more elaborate multimaster systems ...
Page 14
... ADSP-2191M In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the ADSP-219x processor family. Hardware tools include ADSP-219x PC plug-in cards. Third party software tools include DSP libraries, real-time operating systems, and block diagram design tools. ...
Page 15
... I REV. 0 Additional Information This data sheet provides a general overview of the ADSP-2191M architecture and functionality. For detailed information on the 0.10" core architecture of the ADSP-219x family, refer to the ADSP-219x/2191 DSP Hardware Reference. For details on the instruction set, refer to the ADSP-219x Instruction Set Reference. ...
Page 16
... ADSP-2191M Table 7. Pin Function Descriptions (continued) Pin Type Function PF5 I/O/T Programmable Flags 5/SPI1 Slave Select output 2 (when SPI0 enabled)/Multiplier Select 5 /SPI1SEL2 I (during boot) /MSEL5 I PF4 I/O/T Programmable Flags 4/SPI0 Slave Select output 2 (when SPI0 enabled)/Multiplier Select 4 /SPI0SEL2 I (during boot) /MSEL4 ...
Page 17
... Test Data Output (JTAG). Serial scan output of the boundary scan path. TRST Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after I powerup or held low for proper operation of the ADSP-2191M. The TRST pin has internal pull-down resistor. EMU O Emulation Status (JTAG) ...
Page 18
... ADSP-2191M SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS 1 Parameter V Internal (Core) Supply DDINT Voltage V External (I/O) Supply DDEXT Voltage V High Level Input Voltage IH V Low Level Input Voltage IL T Ambient Operating AMB Temperature 1 Specifications subject to change without notice. ELECTRICAL CHARACTERISTICS 1 Parameter V High Level Output Voltage ...
Page 19
... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-2191M features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid perfor- mance degradation or loss of functionality ...
Page 20
... ADSP-2191M TIMING SPECIFICATIONS This section contains timing information for the DSP’s external signals. Use the exact information given. Do not attempt to derive parameters from the addition or subtraction of other information. While addition or subtraction would yield meaningful results for an individual device, the values given in this datasheet reflect statistical variations and worst cases. Consequently, parameters cannot be added meaningfully to derive longer times. Switching characteristics specify how the processor changes its signals. No control is possible over this timing ...
Page 21
... C K CLKI RESET MSEL 6–0 B YPASS DF CL KOU T REV Figure 8. Clock In and Clock Out Cycle Timing –21– ADSP-2191M ...
Page 22
... ADSP-2191M Programmable Flags Cycle Timing Table 10 and Figure 9 describe Programmable Flag operations. Table 10. Programmable Flags Cycle Timing Parameter Switching Characteristics t Flag Output Delay with Respect to CLKOUT DFO t Flag Output Hold After CLKOUT High HFO Timing Requirement t Flag Input Hold is asynchronous HFI ...
Page 23
... – REV HCLK. CTL Figure 11. External Port Write Cycle Timing –23– ADSP-2191M Min Max 0.5t –4 HCLK 0.5t –3 HCLK 0.5t –4 HCLK 0.5t –3 HCLK 3 t –2+W HCLK 0 0.5t – ...
Page 24
... ADSP-2191M External Port Read Cycle Timing Table 13 and Figure 12 describe external port read operations. For additional information on the ACK signal, see the discussion on page 23. Table 13. External Port Read Cycle Timing 1, 2 Parameter Switching Characteristics Chip Select Asserted to RD Asserted Delay t CSRS ...
Page 25
... BGH Figure 13. External Port Bus Request and Grant Cycle Timing REV. 0 Min 4 –25– ADSP-2191M Max Unit 0. HCLK ...
Page 26
... ADSP-2191M Host Port ALE Mode Write Cycle Timing Table 15 and Figure 14 describe Host port write operations in Address Latch Enable (ALE) mode. For more information on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description Table 15. Host Port ALE Mode Write Cycle Timing ...
Page 27
... DAT A VAL ID VA LID FI RST L AST BYT E BYT E Figure 14. Host Port ALE Mode Write Cycle Timing –27– ADSP-2191M EACH BYT IRST B YTE AD DR ESS ART NEXT ...
Page 28
... ADSP-2191M Host Port ACC Mode Write Cycle Timing Table 16 and Figure 15 describe Host port write operations in Address Cycle Control (ACC) mode. For more information on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description Table 16. Host Port ACC Mode Write Cycle Timing ...
Page 29
... ATA VALI D VAL ID F IRST YTE BYTE Figure 15. Host Port ACC Mode Write Cycle Timing –29– ADSP-2191M EAC H B YTE H ACK FIR ST B YTE AD DR ESS VA LID S TAR T NEX T WORD ...
Page 30
... ADSP-2191M Host Port ALE Mode Read Cycle Timing Table 17 and Figure 16 describe Host port read operations in Address Latch Enable (ALE) mode. For more information on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description Table 17. Host Port ALE Mode Read Cycle Timing ...
Page 31
... ATA VAL RST YTE B YTE Figure 16. Host Port ALE Mode Read Cycle Timing –31– ADSP-2191M FOR EACH BYT FIRST BYT ESS VA LID STA RT NEXT WO RD ...
Page 32
... ADSP-2191M Host Port ACC Mode Read Cycle Timing Table 18 and Figure 17 describe Host port read operations in Address Cycle Control (ACC) mode. For more information on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description Table 18. Host Port ACC Mode Read Cycle Timing ...
Page 33
... ATA D ATA VAL ID VAL ID F IRST YTE BYTE Figure 17. Host Port ACC Mode Read Cycle Timing –33– ADSP-2191M BYT IRST BYT RESS TAR T NEX T WORD ...
Page 34
... ADSP-2191M Serial Ports Table 19 and Figure 18 describe SPORT transmit and receive operations, while Sync operations Table 19. Serial Ports Parameter External Clock Timing Requirements t TFS/RFS Setup Before TCLK/RCLK SFSE t TFS/RFS Hold After TCLK/RCLK HFSE t Receive Data Setup Before RCLK SDRE t Receive Data Hold After RCLK ...
Page 35
... DATA RECEIVE-EXTERNAL CLOCK SAMPLE EDGE RCLK t HFSI RFS t HDRI DR DATA TRANSMIT-EXTERNAL CLOCK SAMPLE EDGE TCLK t HFSI TFS DT TCLK / RCLK TCLK / RCLK Figure 18. Serial Ports –35– ADSP-2191M DRIVE SAMPLE EDGE EDGE t SCLKW t DFSE t HOFSE t t SFSE HFSE t t SDRE HDRE DRIVE SAMPLE EDGE ...
Page 36
... ADSP-2191M EXTERNAL RFS WITH MCE = 1, MFD = 0 RCLK RFS DT LATE EXTERNAL TFS TCLK TFS DT Figure 19. Serial Ports—External Late Frame Sync (Frame Sync Setup > 0.5t EXTERNAL RFS WITH MCE = 1, MFD = 0 RCLK RFS DT LATE EXTERNAL TFS TCLK TFS DT Figure 20. Serial Ports—External Late Frame Sync (Frame Sync Setup < 0.5t ...
Page 37
... LID LID –37– ADSP-2191M Min Max 2t –3 HCLK 2t –3 HCLK 2t –3 HCLK 4t –1 HCLK 2t –3 ...
Page 38
... ADSP-2191M Serial Peripheral Interface (SPI) Port—Slave Timing Table 21 and Figure 22 describe SPI port slave operations. Table 21. Serial Peripheral Interface (SPI) Port—Slave Timing Parameter Switching Characteristics SPISS Assertion to Data Out Active t DSOE SPISS Deassertion to Data High Impedance t DSDHI t SCLK Edge to Data Out Valid (Data Out Delay) ...
Page 39
... INTERNAL UART TRANSMIT INTERRUPT REV. 0 DATA(5–8) STOP DATA(5–8) STOP (1–2) Figure 23. UART Port—Receive and Transmit Timing –39– ADSP-2191M Figure 23 there UART RECEIVE BIT SET BY DATA STOP; CLEARED BY FIFO READ UART TRANSMIT BIT SET BY PROGRAM; CLEARED BY WRITE TO TRANSMIT ...
Page 40
... ADSP-2191M JTAG Test And Emulation Port Timing Table 22 and Figure 24 describe JTAG port operations. Table 22. JTAG Port Timing Parameter Switching Characteristics t TDO Delay from TCK Low DTDO t System Outputs Delay After TCK Low DSYS Timing Requirements t TCK Period TCK t TDI, TMS Setup Before TCK High ...
Page 41
... Output Drive Currents Figure 25 shows typical I-V characteristics for the output drivers of the ADSP-2191M. The curves represent the current drive capability of the output drivers as a function of output voltage 3.65V @ DDEXT OUTPUT CURRENT 0 V DDEXT –20 V DDEXT V OL –40 V DDEXT –60 ...
Page 42
... Environmental Conditions The thermal characteristics in which the DSP is operating influence performance. Thermal Characteristics The ADSP-2191M comes in a 144-lead LQFP or 144-lead Ball Grid Array (mini-BGA) package. The ADSP-2191M is specified for an ambient temperature (T formula below. To ensure that the T a heatsink and/or an air flow source may be used. A heatsink 26) ...
Page 43
... PD is shown under Power Dissipation). = Value from CA For the LQFP package: For the mini-BGA package: Table 24. Values CA Airflow 200 250 (Linear Ft./Min.) Airflow (Meters/Second) LQFP: (°C/W) CA Mini-BGA: (°C/W) CA –43– ADSP-2191M Table 24. = 0.96°C 8.4°C 100 200 400 600 0 0 44.3 41.4 38.5 35.3 32.1 ...
Page 44
... ADSP-2191M 144-Lead LQFP Pinout Table 25 lists the LQFP pinout by signal name. the LQFP pinout by pin. Table 25. 144-Lead LQFP Pins (Alphabetically by Signal) Pin Signal No. Signal A0 84 BYPASS A1 85 CLKIN A2 86 CLKOUT A10 ...
Page 45
... V DDINT 112 BR 83 OPMODE 113 BMS 84 A0 114 IOMS 85 A1 115 MS0 86 A2 116 MS1 87 A3 –45– ADSP-2191M Pin No. Signal 117 MS2 118 V DDEXT 119 MS3 120 ACK 121 WR 122 RD 123 D0 124 D1 125 D2 126 D3 127 V DDINT 128 D4 129 GND ...
Page 46
... ADSP-2191M 144-Lead Mini-BGA Pinout Table 27 lists the mini-BGA pinout by signal name. lists the mini-BGA pinout by ball number. Table 27. 144-Lead Mini-BGA Pins (Alphabetically by Signal) Ball Signal No. Signal A0 J11 BYPASS A1 H9 CLKIN A2 H10 CLKOUT A3 G12 D0 A4 H11 D1 A5 G10 D2 A6 F12 D3 A7 G11 ...
Page 47
... HWR DDINT G10 A5 K3 PF6 G11 A7 K4 TMR0 G12 A3 K5 TCLK2 HCMS H1 K6 RXD H2 HA16 K7 RCLK0 H3 HACK K8 RFS0 –47– ADSP-2191M Ball No. Signal K9 DR1 K10 TMS K11 TCK K12 TDI L1 PF1 L2 PF3 L3 PF5 L4 TMR1 L5 DR2 L6 GND L7 DR0 L8 DT1 L9 BMODE1 L10 ...
Page 48
... ADSP-2191M 144-LEAD METRIC THIN PLASTIC QUAD FLATPACK (LQFP) (ST-144) SEATING PLANE 0.08 MAX LEAD COPLANARITY 0.15 0.05 1.60 MAX DETAIL A NOTES: 1. DIMENSIONS IN MILLIMETERS. 2. ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 OF ITS IDEAL POSITION, WHEN MEASURED IN THE LATERAL DIRECTION. 3. CENTER DIMENSIONS ARE NOMINAL. 10.10 10.00 SQ TOP VIEW 1.70 MAX NOTES: 1. DIMENSIONS IN MILLIMETERS. ...
Page 49
... ST = Plastic Thin Quad Flatpack (LQFP Mini Ball Grid Array REV. 0 ORDERING GUIDE Instruction Package Rate (MHz) Description 160 144-Lead LQFP 140 144-Lead LQFP 160 144-Ball Mini-BGA 2.5 Int./3.3 Ext. V 140 144-Ball Mini-BGA 2.5 Int./3.3 Ext. V –49– ADSP-2191M Operating Voltage 2.5 Int./3.3 Ext. V 2.5 Int./3.3 Ext. V ...
Page 50
... ADSP-2191M –50– REV. 0 ...
Page 51
... REV. 0 –51– ADSP-2191M ...
Page 52
PRINTED IN U.S.A. C02936-0-4/02(0) ...