ADSP-BF531WBBCZ-4A AD [Analog Devices], ADSP-BF531WBBCZ-4A Datasheet - Page 13

• Manufacturer Part Number: ADSP-BF531WBBCZ-4A
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

The power dissipated by a processor is largely a function of the
clock frequency of the processor and the square of the operating
voltage. For example, reducing the clock frequency by 25%
results in a 25% reduction in dynamic power dissipation, while
reducing the voltage by 25% reduces dynamic power dissipation
by more than 40%. Further, these power savings are additive, in
that if the clock frequency and supply voltage are both reduced,
the power savings can be dramatic.
The dynamic power management feature of the ADSP-BF531/
ADSP-BF532 processor allows both the processor’s input volt-
age (V
controlled.
The savings in power dissipation can be modeled using the
power savings factor and % power savings calculations.
The power savings factor is calculated as:
where the variables in the equations are:
The percent power savings is calculated as:
VOLTAGE REGULATION
The Blackfin processor provides an on-chip voltage regulator
that can generate processor core voltage levels 0.85 V to 1.2 V
from an external 2.25 V to 3.6 V supply.
ical external components required to complete the power
management system.
voltage levels and is programmable with the voltage regulator
control register (VR_CTL) in increments of 50 mV. To reduce
standby power consumption, the internal voltage regulator can
be programmed to remove power to the processor core while
keeping I/O power (V
V
buffers. The voltage regulator can be activated from this power-
down state either through an RTC wakeup or by asserting
RESET, which will then initiate a boot sequence. The regulator
can also be disabled and bypassed at the user’s discretion.
CLOCK SIGNALS
The ADSP-BF531/ADSP-BF532 processor can be clocked by an
external crystal, a sine wave input, or a buffered, shaped clock
derived from an external clock oscillator.
†
See EE-228: Switching Regulator Design Considerations for Blackfin Processors.
DDEXT
f
f
V
V
t
t
% power savings
CCLKNOM
CCLKRED
NOM
RED
can still be applied, eliminating the need for external
DDINT
DDINTNOM
DDINTRED
is the duration running at f
is the duration running at f
) and clock frequency (f
power savings factor
=
is the reduced core clock frequency
is the nominal core clock frequency
is the reduced internal supply voltage
-------------------- -
f
f
is the nominal internal supply voltage
CCLKNOM
CCLKRED
†
DDEXT
=
The regulator controls the internal logic
) supplied. While in hibernation,
1 power savings factor
⎛
⎝
------------------------- -
V
V
–
DDINTNOM
DDINTRED
CCLK
CCLKRED
CCLKNOM
) to be dynamically
⎞
⎠
2
Figure 6
⎛
⎝
---------- -
t
t
NOM
RED
shows the typ-
⎞
⎠
Rev. D | Page 13 of 60 | August 2006
100%
If an external clock is used, it must not be halted, changed, or
operated below the specified frequency during normal opera-
tion. This signal is connected to the processor’s CLKIN pin.
When an external clock is used, the XTAL pin must be left
unconnected.
Alternatively, because the ADSP-BF531/ADSP-BF532 processor
includes an on-chip oscillator circuit, an external crystal may be
used. The crystal should be connected across the CLKIN and
XTAL pins, with two capacitors connected as shown in
Capacitor values are dependent on crystal type and should be
specified by the crystal manufacturer. A parallel-resonant,
fundamental frequency, microprocessor-grade crystal should
be used.
As shown in
system peripheral clock (SCLK) are derived from the input
clock (CLKIN) signal. An on-chip PLL is capable of multiplying
the CLKIN signal by a user programmable 0.5 to 64 multipli-
cation factor (bounded by specified minimum and maximum
VCO frequencies). The default multiplier is 10 , but it can be
modified by a software instruction sequence. On-the-fly
frequency changes can be effected by simply writing to the
PLL_DIV register.
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
VR
V
V
OU T
D D EX T
D D INT
1–0
Figure 8 on Page
NOTE: VR
AND DESIG NER SHOULD MINIMIZ E TRACE LENGTH TO FDS9431A.
100µF
Figure 7. External Crystal Connections
Figure 6. Voltage Regulator Circuit
CLKIN
100µF
ADSP-BF531/ADSP-BF532
OU T
1µF
1–0 SHOULD BE TIED TOGETHER EXTERNALLY
XTAL
EXTERNAL COMPO NENT S
0.1µF
14, the core clock (CCLK) and
ZHCS1000
10µH
CLKOUT
FDS9431A
2.25V TO 3.6V
INPUT VO LTAGE
RANGE
Figure
7.