ADSP-BF531WBBCZ-4A AD [Analog Devices], ADSP-BF531WBBCZ-4A Datasheet - Page 41

• Manufacturer Part Number: ADSP-BF531WBBCZ-4A
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

Timer Cycle Timing
Table 28
input signal is asynchronous in width capture mode and exter-
nal clock mode and has an absolute maximum input frequency
of f
Table 28. Timer Cycle Timing
1
2
Parameter
Timing Characteristics
t
t
Switching Characteristic
t
The minimum pulse widths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPI_CLK input pins in PWM output mode.
The minimum time for t
WL
WH
HTO
SCLK
/2 MHz.
Timer Pulse Width Input Low
Timer Pulse Width Input High
Timer Pulse Width Output
CLKOUT
(PWM OUTPUT MODE)
EXTERNAL CLOCK MODES)
and
(WIDTH CAPTURE AND
Figure 26
TMRx
TMRx
HTO
is one cycle, and the maximum time for t
describe timer expired operations. The
2
(Measured in SCLK Cycles)
1
1
(Measured in SCLK Cycles)
(Measured in SCLK Cycles)
Rev. D | Page 41 of 60 | August 2006
Figure 26. Timer PWM_OUT Cycle Timing
t
WL
HTO
equals (2
32
–1) cycles.
t
WH
t
HTO
ADSP-BF531/ADSP-BF532
V
Min Max
1
1
1
DDEXT
(2
= 1.8 V V
32
–1) 1
Min
1
1
DDEXT
= 2.5 V/3.3 V
Max
(2
32
–1)
Unit
SCLK
SCLK
SCLK