ADSP-BF531WBBCZ-4A AD [Analog Devices], ADSP-BF531WBBCZ-4A Datasheet - Page 32

• Manufacturer Part Number: ADSP-BF531WBBCZ-4A
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-BF531/ADSP-BF532
Serial Ports
Table 21 on Page 32
on Page 34
operations.
Table 21. Serial Ports—External Clock
1
2
Table 22. Serial Ports—Internal Clock
1
2
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
t
Referenced to sample edge.
Referenced to drive edge.
Referenced to sample edge.
Referenced to drive edge.
SFSE
HFSE
SDRE
HDRE
SCLKEW
SCLKE
DFSE
HOFSE
DDTE
HDTE
SFSI
HFSI
SDRI
HDRI
SCLKEW
SCLKE
DFSI
HOFSI
DDTI
HDTI
SCLKIW
TFS/RFS Setup Before TSCLK/RSCLK
TFS/RFS Hold After TSCLK/RSCLK
Receive Data Setup Before RSCLK
Receive Data Hold After RSCLK
TSCLK/RSCLK Width
TSCLK/RSCLK Period
TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)
TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)
Transmit Data Delay After TSCLK
Transmit Data Hold After TSCLK
TFS/RFS Setup Before TSCLK/RSCLK
TFS/RFS Hold After TSCLK/RSCLK
Receive Data Setup Before RSCLK
Receive Data Hold After RSCLK
TSCLK/RSCLK Width
TSCLK/RSCLK Period
TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)
TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)
Transmit Data Delay After TSCLK
Transmit Data Hold After TSCLK
TSCLK/RSCLK Width
through
Figure 21 on Page 36
through
Table 24 on Page 33
1
1
1
1
1
1
1
1
1
1
describe Serial Port
1
1
and
Rev. D | Page 32 of 60 | August 2006
Figure 19
1
1
2
2
V
Min
3.0
3.0
3.0
3.0
4.5
15.0
0.0
0.0
V
Min
11.0
9.0
0.0
4.5
15.0
4.5
2.0
1.0
2.0
DDEXT
DDEXT
= 1.8 V V
= 1.8 V V
Max
10.0
10.0
Max
3.0
3.0
Min
3.0
3.0
3.0
3.0
4.5
15.0
0.0
0.0
Min
9.0
9.0
0.0
4.5
15.0
4.5
2.0
1.0
2.0
DDEXT
DDEXT
= 2.5 V/3.3 V
= 2.5 V/3.3 V
Max
10.0
10.0
Max
3.0
3.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns