SAA7374GP PHILIPS [NXP Semiconductors], SAA7374GP Datasheet - Page 13
![no-image](/images/no-image-200.jpg)
SAA7374GP
Manufacturer Part Number
SAA7374GP
Description
Low voltage digital servo processor and Compact Disc decoder CD7LV
Manufacturer
PHILIPS [NXP Semiconductors]
Datasheet
1.SAA7374GP.pdf
(60 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SAA7374GP
Manufacturer:
NXPLIPS
Quantity:
247
Part Number:
SAA7374GP
Manufacturer:
PHILIPS/飞利浦
Quantity:
20 000
Philips Semiconductors
7.6
The SAA7374 has a 8 frame FIFO. The error corrector is
a t = 2, e = 4 type, with error corrections on both C1
(32 symbol) and C2 (28 symbol) frames. Four symbols are
used from each frame as parity symbols. This error
corrector can correct up to two errors on the C1 level and
up to four errors on the C2 level.
The error corrector also contains a flag processor. Flags
are assigned to symbols when the error corrector cannot
ascertain if the symbols are definitely good. C1 generates
output flags which are read after (de-interleaving) by C2,
to help in the generation of C2 output flags.
The C2 output flags are used by the interpolator for
concealment of uncorrectable errors. They are also output
via the EBU signal (DOBM) and the EF output with I
for CD-ROM applications.
1998 Feb 26
handbook, full pagewidth
Low voltage digital servo processor and
Compact Disc decoder (CD7LV)
n = disc speed
FIFO and error corrector
F8
W96
33.9/n s
200/n s
min
11.3/n
Fig.8 Subcode format and timing on pin V4.
F1
s
1
11.3/n
F2
Fig.9 Flag output timing diagram.
Q
s
F3
R
2
S-bus
F4
S
F5
13
T
7.6.1
The flags output pin CFLG (open-drain) shows the status
of the error corrector and interpolator and is updated every
frame (7.35
present on the CFLG pin as illustrated in Fig.9. This signal
shows the status of the error corrector and interpolator.
The first flag bit, F1, is the absolute time sync signal, the
FIFO-passed subcode sync and relates the position of the
subcode sync to the audio data (DAC output). This flag
may also be used in a super FIFO or in the synchronization
of different players. The output flags can be made
available at bit 4 of the EBU data format (LSB of the 24-bit
data word), if selected by register A.
F6
U
F7
V
F
F8
LAGS OUTPUT
W
n kHz). In the SAA7374 chip a 1-bit flag is
33.9/n s
11.3/n s min
90/n s max
(CFLG)
MBG425
F1
1
MBG401
Q
Product specification
SAA7374