SAA7374GP PHILIPS [NXP Semiconductors], SAA7374GP Datasheet - Page 8

• Manufacturer Part Number: SAA7374GP
• Description: Low voltage digital servo processor and Compact Disc decoder CD7LV
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
7
7.1
7.1.1
The decoding part can operate at different disc speeds,
from single-speed (n = 1) up to double-speed (n = 2). The
factor ‘n’ is called the overspeed factor. A simplified data
flow through the decoder part is illustrated in Fig.6.
7.1.2
The SAA7374 is a multi-speed decoding device, with an
internal phase-locked loop (PLL) clock multiplier.
Depending on the crystal frequency used and the internal
clock settings (selectable via register B), the playback
speeds shown in Table 1 are possible, where ‘n’ is the
overspeed factor.
An internal clock multiplier is present, controlled by
SELPLL, and should only be used if an 8.4672 MHz
crystal, ceramic resonator or external clock is present.
7.1.3
For high speed CD-ROM applications, the SAA7374 has a
special mode, the lock-to-disc mode. This allows Constant
Angular Velocity (CAV) disc playback with varying input
data rates from the inside-to-outside of the disc. In the
lock-to-disc mode, the FIFO is blocked and the decoder
will adjust its output data rate to the disc speed. Hence, the
frequency of the I
dependent on the disc speed.
In the lock-to-disc mode there is a limit on the maximum
variation in disc speed that the SAA7374 will follow.
Table 1 Playback speeds
Note
1. The CL11 output is always a 5.6448 MHz clock if a 16.9344 MHz external clock is used.
1998 Feb 26
Low voltage digital servo processor and
Compact Disc decoder (CD7LV)
REGISTER B
FUNCTIONAL DESCRIPTION
Decoder part
00xx
00xx
01xx
10xx
10xx
11xx
P
D
L
OCK
RINCIPLE OPERATIONAL MODES OF THE DECODER
ECODING SPEED AND CRYSTAL FREQUENCY
-
TO
-
2
DISC MODE
S-bus (WCLK and SCLK) clocks are
SELPLL
0
1
0
0
1
0
33.8688
n = 1
n = 2
CRYSTAL FREQUENCY (MHz)
8
Disc speeds must always be within 25 to 100% range of
their nominal value. The lock-to-disc mode is
enabled/disabled by register E.
7.1.4
The SAA7374 may be placed in two standby modes
selected by register B (it should be noted that the device
core is still active)
In the standby modes the various pins will have the
following values;
Standby 1: “CD-STOP” mode. Most I/O functions are
switched off.
Standby 2: “CD-PAUSE” mode. Audio output features
are switched off, but the motor loop, the motor output
and the subcode interfaces remain active. This is also
called a “Hot Pause”.
MOTO1 and MOTO2: put in high-impedance, PWM
mode (standby 1 and reset, operating in standby 2).
Put in high-impedance, PDM mode (standby 1 and
reset, operating in standby 2).
SCL, SDA, SILD and RAB: no interaction. Normal
operation continues.
SCLK, WCLK, DATA, EF, CL11 and DOBM: 3-state in
both standby modes. Normal operation continues after
reset.
CRIN, CROUT, CL16 and CL4: no interaction. Normal
operation continues.
V1, V2, V3, V4, V5, CFLG and C2FAIL: no interaction.
Normal operation continues.
16.9344
n = 1
n = 2
S
TANDBY MODES
8.4672
n = 1
n = 2
Product specification
FREQUENCY
SAA7374
(MHz)
11.2896
11.2896
11.2896
11.2896
5.6448
5.6448
CL11
(1)