AD14160KB-4 AD [Analog Devices], AD14160KB-4 Datasheet - Page 2

• Manufacturer Part Number: AD14160KB-4
• Description: Quad-SHARC DSP Multiprocessor Family
• Manufacturer: AD [Analog Devices]

AD14160/AD14160L
DETAILED DESCRIPTION
Architectural Features
ADSP-21060 Core
The AD14160/AD14160L is based on the powerful ADSP-21060
(SHARC) DSP chip. The ADSP-21060 SHARC combines a
high performance floating-point DSP core with integrated, on-
chip system features including a 4 Mbit SRAM memory, host
processor interface, DMA controller, serial ports, and both link
port and parallel bus connectivity for glueless DSP multiprocess-
ing, (see Figure 1). It is fabricated in a high speed, low power
CMOS process, and has a 25 ns instruction cycle time. The arith-
metic/ logic unit (ALU), multiplier and shifter all perform single-
cycle instructions, and the three units are arranged in parallel,
maximizing computational throughput.
The SHARC features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data, and the pro-
gram memory (PM) bus transfers both instructions and data.
There is also an on-chip instruction cache which selectively
caches only those instructions whose fetches conflict with the
PM bus data accesses. This combines with the separate program
and data memory buses to enable three-bus operation for fetch-
ing an instruction and two operands, all in a single cycle. The
SHARC also contains a general purpose data register file, which
MULTIPLIER
8 x 4 x 32
DAG1
CONNECT
BUS
(PX)
8 x 4 x 24
DAG2
Figure 1. ADSP-21060 Processor Block Diagram (Core of the AD14160/AD14160L)
CORE PROCESSOR
REGISTER
16 x 40-BIT
DATA
PM ADDRESS BUS
FILE
DM ADDRESS BUS
TIMER
PM DATA BUS
DM DATA BUS
BARREL
SHIFTER
SEQUENCER
PROGRAM
INSTRUCTION
32 x 48-BIT
CACHE
48
40/32
24
32
ALU
ADDR
PROCESSOR PORT
ADDR
–2–
DUAL-PORTED SRAM
DUAL-PORTED BLOCKS
is a 10-port, 32-register (16 primary, 16 secondary) file. Each
SHARC’s core also implements two data address generators
(DAGs), implementing circular data buffers in hardware. The
DAGs contain sufficient registers to allow the creation of up to
32 circular buffers. The 48-bit instruction word accommodates a
variety of parallel operations, for concise programming. For ex-
ample, the ADSP-21060 can conditionally execute a multiply, an
add, a subtract, and a branch, all in a single instruction.
The SHARCs contain 4 Mbits of on-chip SRAM each, orga-
nized as two blocks of 2 Mbits, which can be configured for
different combinations of code and data storage. The memory
can be configured as a maximum of 128K words of 32-bit data,
256K words of 16-bit data, 80K words of 48-bit instructions (or
40-bit data), or combinations of different word sizes up to
4 megabits. A 16-bit floating-point storage format is supported
which effectively doubles the amount of data that may be stored
on chip. Conversion between the 32-bit floating point and 16-
bit floating point formats is done in a single instruction. Each
memory block is dual-ported for single-cycle, independent
accesses by the core processor and I/O processor or DMA con-
troller. The dual-ported memory and separate on-chip buses
allow two data transfers from the core and one from I/O, all in a
single cycle.
DATA
TWO INDEPENDENT
(
DATA BUFFERS
MEMORY MAPPED)
DATA
STATUS, AND
REGISTERS
CONTROL,
IOP
DATA
I/O PROCESSOR
I/O PORT
DATA
IOD
48
ADDR
SERIAL PORTS
CONTROLLER
LINK PORTS
ADDR
IOA
17
DMA
(2)
(6)
MULTIPROCESSOR
EXTERNAL
INTERFACE
ADDR BUS
HOST PORT
DATA BUS
36
6
6
PORT
4
MUX
MUX
EMULATION
TEST AND
JTAG
32
48
7
REV. A