AD14160KB-4 AD [Analog Devices], AD14160KB-4 Datasheet - Page 30

• Manufacturer Part Number: AD14160KB-4
• Description: Quad-SHARC DSP Multiprocessor Family
• Manufacturer: AD [Analog Devices]

AD14160/AD14160L
Link Ports: 1
Parameter
Receive
Timing Requirements:
t
t
t
t
t
Switching Characteristics:
t
t
t
t
Transmit
Timing Requirements:
t
t
Switching Characteristics:
t
t
t
t
t
t
t
t
Link Port Service Request Interrupts: 1
Timing Requirements:
t
t
NOTES
1
2
2
SLDCL
HLDCL
LCLKIW
LCLKRWL
LCLKRWH
DLAHC
DLALC
ENDLK
TDLK
SLACH
HLACH
DLCLK
DLDCH
HLDCH
LCLKTWL
LCLKTWH
DLACLK
ENDLK
TDLK
SLCK
HLCK
LACK will go low with t
Only required for interrupt recognition in the current cycle.
Speed Operations
Data Setup Before LCLK Low
Data Hold After LCLK Low
LCLK Period (1
LCLK Width Low
LCLK Width High
LACK High Delay After CLKIN High
LACK Low Delay After LCLK High
LACK Enable from CLKIN
LACK Disable from CLKIN
LACK Setup Before LCLK High
LACK Hold After LCLK High
LCLK Delay After CLKIN (1
Data Delay After LCLK High
Data Hold After LCLK High
LCLK Width Low
LCLK Width High
LCLK Low Delay After LACK High
LDAT, LCLK Enable After CLKIN
LDAT, LCLK Disable After CLKIN
LACK/LCLK Setup Before CLKIN Low
LACK/LCLK Hold After CLKIN Low
CLK Speed Operation
DLALC
relative to rising edge of LCLK after first nibble is received. LACK will not go low if the receiver’s link buffer is not about to fill.
Operation)
Operation)
and
1
2
2
Min
3.5
3
t
6
5
18 + DT/2
–3
5 + DT/2
18
–7
–3
(t
(t
(t
5 + DT/2
10
2
CK
CK
CK
CK
/2) – 2
/2) – 2
/2) + 8.5 (3
–30–
40 MHz–5 V
Max
29 + DT/2
13.5
20.5 + DT/2
16
3.5
(t
(t
20.5 + DT/2
CK
CK
/2) + 2
/2) + 2
t
CK
/2) + 17.5
Min
3
3
t
6
5
18 + DT/2
–3
5 + DT/2
20
–7
–3
(t
(t
(t
5 + DT/2
10
2
CK
CK
CK
CK
/2) – 1
/2) – 1.25
/2) + 8
40 MHz–3.3 V
Max
29 + DT/2
13.5
20.5 + DT/2
17
3
(t
(t
(3
20.5 + DT/2
CK
CK
/2) + 1.25
/2) + 1
t
CK
/2) + 18 ns
REV. A
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns