AD14160KB-4 AD [Analog Devices], AD14160KB-4 Datasheet - Page 37

• Manufacturer Part Number: AD14160KB-4
• Description: Quad-SHARC DSP Multiprocessor Family
• Manufacturer: AD [Analog Devices]

OUTPUT DRIVE CURRENTS
Figure 26 shows typical I-V characteristics for the output drivers
of the ADSP-2106x. The curves represent the current drive
capability of the output drivers as a function of output voltage.
REV. A
Figure 27. ADSP-2106x Typical Drive Currents (V
Figure 26. ADSP-2106x Typical Drive Currents (V
–100
–120
–100
–125
–150
–175
–200
120
100
–20
–40
–60
–80
100
–25
–50
–75
80
60
40
20
75
50
25
0
0
0
0
3.0V, +85 C
0.75
0.5
5.25V, –40 C
1.50
1
SOURCE VOLTAGE – V
SOURCE VOLTAGE – V
V
V
OH
OL
4.75V, +85
3.0V, +85
3.3V, +25
5.0V, +25
2.25
1.5
5.0V, +25
°
°
C
C
°
°
3.00
C
3.3V, +25
C
2
°
4.75V, +85
C
3.6V, –40
3.75
2.5
°
3.6V, –40
C
5.25V, –40
°
C
°
4.50
C
°
3
C
°
C
DD
DD
5.25
3.5
= 3.3 V)
= 5 V)
–37–
POWER DISSIPATION
Total power dissipation has two components, one due to inter-
nal circuitry and one due to the switching of external output
drivers. Internal power dissipation is dependent on the instruc-
tion execution sequence and the data operands involved. Inter-
nal power dissipation is calculated in the following way:
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
and is calculated by:
The load capacitance should include the processor’s package
capacitance (C
load high and then back low. Address and data pins can drive
high and low at a maximum rate of 1/(2t
can switch every cycle at a frequency of 1/t
at 1/(2t
Example:
Estimate P
The P
drive:
Pin
Type
Address
MS0
WR
Data
ADRCLK
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation:
Note that the conditions causing a worst-case P
from those causing a worst-case P
occur while 100% of the output pins are switching from all ones
to all zeros. Also note that it is not common for an application to
have 100% or even 50% of the outputs switching simultaneously.
– the number of output pins that switch during each cycle (O)
– the maximum frequency at which they can switch (f)
– their load capacitance (C)
– their voltage swing (V
–A system with one bank of external data memory RAM
–Four 128K 8 RAM chips are used, each with a load of 10 pF.
–External data memory writes occur every other cycle, a rate
–of 1/(4t
–The instruction cycle rate is 40 MHz (t
–V
(32-bit).
DD
EXT
CK
= 3.3 V.
), but selects can switch on each cycle.
equation is calculated for each class of pins that can
EXT
CK
# of
Pins
15
1
1
32
1
), with 50% of the pins switching.
IN
with the following assumptions:
P
). The switching frequency includes driving the
TOTAL
%
Switching
50
0
–
50
–
P
EXT
= P
P
INT
= O
DD
EXT
AD14160/AD14160L
)
= I
55 pF
55 pF
55 pF
25 pF
15 pF
+ (I
C
DDIN
C
INT
DDIN2
V
. Maximum P
DD
V
20 MHz
40 MHz
20 MHz
20 MHz
40 MHz
DD
2
CK
5.0 V )
CK
). The write strobe
f
CK
. Select pins switch
P
EXT
= 25 ns) and
P
EXT
EXT
10.9 V = 0.089 W
10.9 V = 0.00 W
10.9 V = 0.024 W
10.9 V = 0.087 W
10.9 V = 0.007 W
V
(3.3 V)= 0.207 W
INT
DD
(5 V)= 0.476 W
are different
2
cannot
= P
EXT