AD14160KB-4 AD [Analog Devices], AD14160KB-4 Datasheet - Page 20

• Manufacturer Part Number: AD14160KB-4
• Description: Quad-SHARC DSP Multiprocessor Family
• Manufacturer: AD [Analog Devices]

AD14160/AD14160L
Synchronous Read/Write—Bus Master
Use these specifications for interfacing to external memory
systems that require CLKIN—relative timing or for accessing a
slave ADSP-2106x (in multiprocessor memory space). These
synchronous switching characteristics are also valid during asyn-
chronous memory reads and writes (see Memory Read—Bus
Master and Memory Write—Bus Master).
Parameter
Timing Requirements:
t
t
t
t
t
Switching Characteristics:
t
t
t
t
t
t
t
t
t
t
t
t
W = (number of Wait states specified in WAIT register)
NOTES
1
2
3
SSDATI
HSDATI
DAAK
SACKC
HACKC
DADRO
HADRO
DPGC
DRDO
DWRO
DRWL
SDDATO
DATTR
DADCCK
ADRCK
ADRCKH
ADRCKL
For MSx, SW, BMS, the falling edge is referenced.
ACK Delay/Setup: User must meet t
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
Data Setup Before CLKIN
Data Hold After CLKIN
ACK Delay After Address,
MSx, SW, BMS
ACK Setup Before CLKIN
ACK Hold After CLKIN
Address, MSx, BMS, SW Delay
After CLKIN
Address, MSx, BMS, SW Hold
After CLKIN
PAGE Delay After CLKIN
RD High Delay After CLKIN
WR High Delay After CLKIN
RD/WR Low Delay After CLKIN
Data Delay After CLKIN
Data Disable After CLKIN
ADRCLK Delay After CLKIN
ADRCLK Period
ADRCLK Width High
ADRCLK Width Low
1
1, 2
DAAK
or t
3
DSAK
2
or synchronous specification t
t
CK
Min
3.5 + DT/8
3.5 – DT/8
7 + DT/4
–1 – DT/4
–1 – DT/8
9 + DT/8
–2 – DT/8
–3 – 3DT/16
0 – DT/8
4 + DT/8
t
(t
(t
.
8 + DT/4
CK
CK
CK
/2 – 2)
/2 – 2)
40 MHz–5 V
–20–
SACKC
Max
13 + 7 DT/8 + W
8 – DT/8
16.5 + DT/8
5 – DT/8
5 – 3DT/16
13.5 + DT/4
20 + 5DT/16
8 – DT/8
10.5 + DT/8
When accessing a slave ADSP-2106x, these switching character-
istics must meet the slave’s timing requirements for synchronous
read/writes (see Synchronous Read/Write—Bus Slave). The
slave ADSP-2106x must also meet these (bus master) timing
requirements for data and acknowledge setup and hold times.
.
Min
3.5 + DT/8
3.5 – DT/8
7 + DT/4
–1 – DT/4
–1 – DT/8
9 + DT/8
–2 – DT/8
–3 – 3DT/16
0 – DT/8
4 + DT/8
t
(t
(t
8 + DT/4
CK
CK
CK
/2 – 2)
/2 – 2)
40 MHz–3.3 V
13 + 7 DT/8 + W
8 – DT/8
16.5 + DT/8
5 – DT/8
5 – 3DT/16
13.5 + DT/4
20 + 5DT/16
8 – DT/8
10.5 + DT/8
Max
REV. A
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns