AD14160KB-4 AD [Analog Devices], AD14160KB-4 Datasheet - Page 25

• Manufacturer Part Number: AD14160KB-4
• Description: Quad-SHARC DSP Multiprocessor Family
• Manufacturer: AD [Analog Devices]

Parameter
Lead Cycle
Timing Requirements:
t
t
t
t
t
Switching Characteristics:
t
t
t
t
Write Cycle
Timing Requirements:
t
t
t
t
t
t
t
t
t
Switching Characteristics:
t
t
t
NOTE
1
REV. A
Asynchronous Read/Write—Host to AD14160/AD14160L
Use these specifications for asynchronous host processor accesses
of an AD14160/AD14160L, after the host has asserted CS and
HBR (low). After HBG is returned by the AD14160/AD14160L,
SADRDL
HADRDH
WRWH
DRDHRDY
DRDHRDY
SDATRDY
DRDYRDL
RDYPRD
HDARWH
SCSWRL
HCSWRH
SADWRH
HADWRH
WWRL
WRWH
DWRHRDY
SDATWH
HDATWH
DRDYWRL
RDYPWR
SRDYCK
Not required if RD and address are valid t
or WR goes low or by t
driven during asynchronous host accesses, see Table 8.2 of the ADSP-2106x SHARC User’s Manual.
Address Setup/CS Low Before RD Low
Address Hold/CS Hold Low After RD
RD/WR High Width
RD High Delay After REDY (O/D) Disable
RD High Delay After REDY (A/D) Disable
Data Valid Before REDY Disable from Low
REDY (O/D) or (A/D) Low Delay After RD Low
REDY (O/D) or (A/D) Low Pulsewidth for Read
Data Disable After RD High
CS Low Setup Before WR Low
CS Low Hold After WR High
Address Setup Before WR High
Address Hold After WR High
WR Low Width
RD/WR High Width
WR High Delay After REDY (O/D) or (A/D) Disable
Data Setup Before WR High
Data Hold After WR High
REDY (O/D) or (A/D) Low Delay After WR/CS Low
REDY (O/D) or (A/D) Low Pulsewidth for Write
REDY (O/D) or (A/D) Disable to CLKIN
HBGRCSV
after HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. For address bits to be
REDY (A/D)
REDY (O/D)
HBGRCSV
CLKIN
after HBG goes low. For first access after HBR asserted, ADDR
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
Figure 19a. Synchronous REDY Timing
1
Min
1
1
6
1
45 + DT
2
0
0.5
6
2.5
7
6
0.5
6
1.5
0.5
0.5
15
0.5 + 7DT/16 8 + 7DT/16
–25–
the host can drive the RD and WR pins to access the AD14160/
AD14160L’s internal memory or IOP registers. HBR and HBG
are assumed low for this timing.
40 MHz–5 V
Max
11
9.5
11
t
SRDYCK
31–0
Min
1
1
6
1
45 + DT
2
0
0.5
6
2.5
7
6
0.5
6
1.5
0.5
0.5
15
0.5 + 7DT/16
must be a non-MMS value 1/2 t
AD14160/AD14160L
40 MHz–3.3 V
Max
11.5
10
11.5
8 + 7DT/16
CLK
before RD
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns