STA2500DTR STMICROELECTRONICS [STMicroelectronics], STA2500DTR Datasheet
STA2500DTR
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STA2500DTR Summary of contents
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... Ciphering support up to 128-bit key ■ Single power supply with internal regulators for core voltage generation ■ Supports 1. 2.85 V I/O systems ■ Auto calibration (VCO, filters) Table 1. Device summary Order code STA2500D STA2500DTR Doc ID 16067 Rev 1 STA2500D Package Packing Tray LFBGA48 Tape and reel 1/57 www.st.com 1 ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STA2500D 6.8 Clock request signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STA2500D List of figures Figure 1. Block diagram and electrical schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Description 1 Description The STA2500D is a single chip Bluetooth solution that is fully optimized for automotive applications such as telematics, navigation and portable navigation. Power consumption levels are targeted at battery powered devices and single chip solution brings cost ...
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STA2500D 2 Quick reference data BT_VIO_x means BT_VIO_A, BT_VIO_B. BT_HVx means BT_HVA, BT_HVD. (See also Table 13.) 2.1 Absolute maximum ratings The absolute maximum rating (AMR) corresponds to the maximum value that can be applied without leading to instantaneous or ...
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Quick reference data 2.3 I/O specifications The I/Os comply with the EIA/JEDEC standard JESD8-B. Table 4. DC input specification Symbol V IL_BT Low level input voltage V High level input voltage IH_BT (1) C Input capacitance in_BT R Pull-up equivalent ...
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STA2500D Table 8. System clock, sine wave specifications Symbol V Peak to peak voltage range PP N Total harmonic content of input signal H Z Real part of parallel input impedance at pin INRe Z Imaginary part of parallel input ...
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Quick reference data Table 11. Low power clock specifications (continued) The low power clock pin is powered by connecting BT_VIO_B to the wanted supply. Symbol Parameter V Schmitt trigger hysteresis (BT_VIO_B = 1.3 V) hyst C Input capacitance IN T ...
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STA2500D Table 12. Current consumption Active: data (DH5) Master or Slave (723.2 kbps asymmetrical in TX mode) (433.9 kbps symmetrical) Active: data (2-DH5) Master or Slave (869.7 kbps symmetrical) Active: data (3-DH5) Master or Slave (1306.9 kbps symmetrical) Active: audio ...
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Block diagram and electrical schematic 3 Block diagram and electrical schematic Figure 1. Block diagram and electrical schematic BT_RFP Filter BT_RFN BT_REF_CLK_IN 12/57 BT_VDD[4:0] BT_HV[1:0] INTERNAL SUPPLY MANAGEMENT DEMO- RECEIVER DULATOR CONTROL RF PLL AND Fractional N REGISTER BASEBAND CORE ...
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STA2500D 4 Pinout Figure 2. Pinout (bottom view 4.1 Pin description and assignment Table 13 shows the pin list of the STA2500D. In columns “Reset” and “Default after reset”, the “PD/PU” shows the ...
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Pinout For the output pin the default drive capability is 2 mA, except for pin K3 (BT_GPIO_11) and pin L3 (BT_GPIO_8) where such that when used for Class 1, these 2 pins can be used for ...
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STA2500D Table 13. The STA2500D pin list (functional and supply) (continued) Pin Name # BT_GPIO_11 B2 JTAG_TDO or GPIO BT_GPIO_10 C1 JTAG_TMS or GPIO JTAG_NTRST (Active low) or Alternate BT_GPIO_16 B3 function. BT_GPIO_8 C3 JTAG_TCK or GPIO General purpose input/output ...
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Pinout Table 13. The STA2500D pin list (functional and supply) (continued) Pin Name # Internal supply decoupling/Regulator output. BT_VDD_D G2 Need 220nF decoupling capacitor to BT_VSSDIG. Internal supply decoupling/Regulator output. BT_VDD_DSM B7 Need 220nF decoupling capacitor to BT_VSSANA. Internal supply ...
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STA2500D Table 14. Configuration programming BT_CONFIG_1 BT_CONFIG_2 BT_CONFIG_3 order to get other SPI modes, the Host must send a specific configuration at ...
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Functional description 5 Functional description 5.1 Transmitter The transmitter uses the serial transmit data from the Bluetooth Controller. The transmitter modulator converts this data into GFSK, π/4-DQPSK or 8-DPSK modulated I and Q digital signals for respectively 1, 2 and ...
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STA2500D 5.4 Bluetooth controller V1.2 and V2.0 + EDR features The Bluetooth controller is backward compatible with the Bluetooth specification V1.2 [] and V2.0 + EDR []. Here below is a list with the main features of those specifications: ● ...
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Functional description 5.7 TX output power control The STA2500D supports output power control with advanced features: ● Basic feature: – With the standard TX power control algorithm enabled, the STA2500D will adapt its output power when a remote BT device ...
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STA2500D 6 General specification All the values are provided according to the Bluetooth specification V2.1 + EDR (“Lisbon”) unless otherwise specified. The below values are preliminary and will be updated in the next version of this datasheet. 6.1 Receiver All ...
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General specification Table 16. Mbps receiver parameters - GFSK (continued) Symbol Parameter C/I Adjacent (-3 MHz) interference -3MHz Adjacent (≥ ±4 MHz) C/I ≥4MHz interference Receiver inter-modulation IMD Inter-modulation Typical is defined at T over corner lots and temperature. Parameters ...
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STA2500D Mbps receiver parameters - π/4-DQPSK (continued) Table 17. Symbol Parameter C/I Adjacent (-3 MHz) interference -3MHz Adjacent (≥ ±4 MHz) C/I ≥4MHz interference Typical is defined at T over corner lots and temperature. Parameters are given at device pin, ...
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General specification 6.2 Transmitter Unless otherwise stated, typical is defined at T Maximum are worst cases over corner lots and temperature. Parameters are given at device pin, except for in-band spurious measured at antenna. Table 19. Transmitter parameters Symbol Parameter ...
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STA2500D Table 19. Transmitter parameters (continued) Symbol Parameter Initial carrier frequency tolerance (for an exact reference) ΔF |f_TX-f0| (6) Carrier frequency stability |Δf_s| Carrier frequency stability (7) Carrier frequency drift |Δf_p1| One slot packet |Δf_p3| Three slots packet |Δf_p5| Five ...
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General specification 6.3 Class 1 operation The STA2500D supports operation at Class 1 output power levels with the use of an external PA. The operation of the external PA and antenna switch are controlled by the following signals: Table 20. ...
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STA2500D 6.5 System clock The STA2500D works with a sine wave or digital clock provided on the BT_REF_CLK_IN pin. Detailed specifications are found in 6.6 Low power clock The low power clock is used by the Bluetooth Controller as reference ...
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General specification Figure 3. Active high clock request input and output combined with UART or SPI BT_CLK_REQ_IN_1 BT_CLK_REQ_IN_2 (*) BT_CLK_REQ_IN_1 and BT_CLK_REQ_IN_2 are used UNLESS one or both are re-programmed as alternate function(s) via Parameter File ● Active low clock ...
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STA2500D 6.9 Interrupts The user can program the BT_GPIOs as external interrupt sources. 6.10 Low power modes 6.10.1 Overview To save power, three low power modes are supported as described in Depending of the Bluetooth and of the Host's activity, ...
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General specification 6.10.2 Some examples for the usage of the low power modes Sniff or sniff subrating The STA2500D is in active mode with a Bluetooth connection. Once the transmission is concluded, Sniff or Sniff Subrating is programmed. When one ...
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STA2500D available. In this mode, the break function (BT_UART_RXD is low for more than 1 word) is used to distinguish between normal operation and low power mode usage. ● Deep sleep mode entry The Host tells the STA2500D that it ...
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General specification Figure 6. Deep sleep mode entry and wake-up through H4 UART UART on UART on Active Active HOST_WAKEUP =‘ 1’ or ‘ 0’ HOST_WAKEUP =‘ 1’ or ‘ 0’ Deep sleep mode entry and wake-up through enhanced H4 ...
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STA2500D SPI HW block even before the system clock is available. This block will generate an interrupt, allowing the Bluetooth Controller to reply with a WOKEN message. This is illustrated in 2. Autonomous wake-up with communication (i.e. initiated by the ...
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General specification Figure 9. Wake-up by the Bluetooth controller with data transmission to the host, through enhanced H4 SPI SPI_CSN SPI_CLK SPI_DO SPI_DI SPI_INT CLK _REQ _ OUT_1 REF_CLK _IN Deep sleep mode entry and wake-up through H4 SPI It ...
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STA2500D Figure 10. Deep sleep mode entry and wake-up through H4 SPI SPI on SPI on Active Active HOST_WAKEUP =‘ 1’ or ‘ 0’ HOST_WAKEUP =‘ 1’ or ‘ 0’ Deep sleep mode entry and wake-up through H4 UART or ...
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General specification BT_HOST_WAKEUP to ‘1’ in order to warm the Host and traffic starts when the Host puts BT_UART_CTS to low. This is illustrated in 2. Autonomous wake-up with communication (i.e. initiated by the STA2500D) The STA2500D first asks the ...
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STA2500D Figure 12. Wakeup by host through UART with handshake BT_W AK EUP UART_RTS UART_RTS UART_RTS UART_CTS H O ST_W AK EUP CLK _REQ _O UT_1 REF_CLK _IN 5. Host pulls BT_WAKEUP high to wake-up BT Controller. HW starts driving ...
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General specification 6.13 Bluetooth - WLAN coexistence in collocated scenario The coexistence interface uses WLAN control signal pins, which can be mapped via software parameter download on different pins of the STA2500D (see The functionality of the ...
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STA2500D The combination of time division multiplexing and the priority mechanism avoids the interference due to packet collision. It also allows the maximization of the 2.4 GHz ISM bandwidth usage for both devices while preserving the quality of some critical ...
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General specification 6.13.5 Algorithm 5: Alternating wireless medium access (AWMA) AWMA utilizes a portion of the WLAN beacon interval for Bluetooth operations. From a timing perspective, the medium assignment alternates between usage following WLAN procedures and usage following Bluetooth procedures. ...
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STA2500D 7 Digital interfaces 7.1 The UART interface The STA2500D contains a 4-pin (BT_UART_RXD, BT_UART_TXD, BT_UART_RTS, and BT_UART_CTS) UART compatible with 16450, 16550 and 16750 standards running up to 4000 kbps (+1.5% / -1%). The configuration is 8 ...
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Digital interfaces positive edge of SPI_CLK. When SPI_CSN is inactive, this BT Controller output is in tristate mode. ● SPI_DI (on pin BT_UART_RXD/BT_SPI_DI): data transfer from Master to Slave. Data is generated on the negative edge of SPI_CLK by the ...
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STA2500D Figure 18. SPI setup and hold timing Table 26. SPI timing parameters Symbol P SPI_CLK full period CL T High period of SPI_CLK CLH T Low period of SPI_CLK CLL T High period of SPI_CSN CSH T Low period ...
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Digital interfaces In Slave mode, all possible PCM_SYNC lengths are supported (including “short frame” PCM_CLK period) and “long frame” (> 1 PCM_CLK period)). In Master mode, the length is configurable (1 (“short frame”), (“long frame”) ...
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STA2500D Table 27. PCM interface parameters Symbol PCM Interface F Frequency of PCM_CLK (Slave) PCM_CLK F Frequency of PCM_SYNC PCM_SYNC P Delay of the starting of the first slot sync_delay S Slot start (programmable for every slot Data ...
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Digital interfaces 7.4 The JTAG interface The JTAG interface is compliant with the JTAG IEEE Standard 1149.1. It allows both the boundary scan of the digital pins and the debug of the ARM7TDMI application when connected with the standard ARM7 ...
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STA2500D Table 29. Examples of BT_GPIO pin programming (continued) STA2500D Pin Name BT_PCM_B PCM_B BT_GPIO_0 I2C_CLK BT_CLK_REQ_IN_1 I2C_DAT BT_CLK_REQ_IN_2 GPIO_2 BT_HOST_WAKEUP/BT_SPI HOST_WAKEUP _INT BT_GPIO_11 ANT_SWITCH BT_GPIO_9 PA_LEVEL2 BT_GPIO_10 PA_LEVEL1 BT_GPIO_8 RX_ENABLE BT_GPIO_16 PA_ENABLE BT_CLK_REQ_OUT_1 CLK_REQ_OUT_1 CLK_REQ_OUT_1 CLK_REQ_OUT_1 CLK_REQ_OUT_1 BT_CLK_REQ_OUT_2 NA ...
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HCI transport layer 8 HCI transport layer The STA2500D supports the HCI transport layer as defined by the SIG: H4 []. It is supported in combination with UART and SPI mode. The STA2500D also supports an enhanced version of the ...
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STA2500D 8.2 Enhanced H4 SPI transport layer This is the default SPI mode. The enhanced H4 protocol is based on the H4 protocol as defined by the SIG []. In addition a messaging protocol is defined for controlling the Deep ...
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Package information 9 Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ...
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STA2500D Figure 25. Package markings Table 30. Package markings legend Item A Type + version B Assembly Plant C BE sequence (LL) D Assembly Year (Y) E Assembly Week (WW) F Second_lvl_intct G Standard ST Logo H Dot (pin A1) ...
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References 10 References Table 31. References Short ID name [1] - Specification of the Bluetooth System V2.1 + EDR (“Lisbon”) [2] - Specification of the Bluetooth System V2.0 + EDR [3] - Specification of the Bluetooth System V1.2 Specification of ...
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STA2500D 11 Acronyms and abbreviations Table 32. Acronyms and abbreviations Acronyms/ abbreviation 2-DH12- Bluetooth 2 Mbps ACL packet types DH32-DH5 2-EV3 Bluetooth 2 Mbps synchronous packet types 2-EV5 3-DH1 3-DH3 Bluetooth 3 Mbps ACL packet types 3-DH5 3-EV3 Bluetooth 3 ...
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Acronyms and abbreviations Table 32. Acronyms and abbreviations (continued) Acronyms/ abbreviation DEVM Differential Error Vector Amplitude DH1 DH3 Bluetooth 1 Mbps ACL packet types DH5 DM1 DM3 Bluetooth 1 Mbps ACL packet types DM5 DMA Direct Memory Access DV Bluetooth ...
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STA2500D Table 32. Acronyms and abbreviations (continued) Acronyms/ abbreviation π/4-DQPSK π/4 rotated Differential Quaternary Phase Shift Keying PA Power Amplifier PCB Printed Circuit Board PCM Pulse Code Modulation PD Pull-Down PLL Phase Locked Loop PPEC Pitch-Period Error Concealment PTA Packet ...
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Revision history 12 Revision history Table 33. Document revision history Date 24-Jul-2009 56/57 Revision 1 Initial release. Doc ID 16067 Rev 1 STA2500D Changes ...
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STA2500D Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at ...