STA2500DTR STMICROELECTRONICS [STMicroelectronics], STA2500DTR Datasheet - Page 45

• Manufacturer Part Number: STA2500DTR
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

STA2500D
Table 27.
1. Note that it is not possible to use 16 bits in Slave case if pcm_clk is 128kHz. This is the only exception.
2. In Master case, the maximum of PCM_CLK is 2048 kHz.
Table 28.
PCM Interface
F
P
F
PCM_SYNC
Symbol
Symbol
sync_delay
PCM_CLK
t
t
t
t
t
t
t
WCH
WSH
WCL
HCD
DCD
SSC
SDC
S
D
N
s
Frequency of PCM_CLK (Slave)
Frequency of PCM_SYNC
Delay of the starting of the first slot
Slot start (programmable for every slot)
Data size
Number of slots per frame
High period of PCM_CLK
Low period of PCM_CLK
High period of PCM_SYNC
Setup time, PCM_SYNC high to PCM_CLK low
Setup time, PCM_A/B input valid to PCM_CLK low
Hold time, PCM_CLK low to PCM_A/B input valid
Delay time, PCM_CLK high to PCM_A/B output valid
PCM interface parameters
PCM interface timing (at PCM_CLK = 2048 kHz)
Figure 22. PCM interface timing
PCM_B/A out
PCM_SYNC
PCM_A/B in
PCM_CLK
Description
Description
t
WCH
Doc ID 16067 Rev 1
t
WSH
t
WCL
t
SSC
MSB
MSB
MSB-1
t
SDC
MSB-1
t
DCD
MSB-2
MSB-2
128
Min.
Min.
200
200
200
100
100
100
0
0
8
1
-
-
(1)
MSB-3
t
HCD
MSB-3
2048
Typ.
Typ.
8
-
-
-
-
-
-
-
-
-
-
-
MSB-4
D02TL557
MSB-4
Digital interfaces
4000
Max.
Max.
255
255
150
16
3
-
-
-
-
-
-
-
(2)
cycles
cycles
Unit
Unit
kHz
kHz
bits
ns
ns
ns
ns
ns
ns
ns
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