STA2500DTR STMICROELECTRONICS [STMicroelectronics], STA2500DTR Datasheet - Page 26

• Manufacturer Part Number: STA2500DTR
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

General specification
6.3
6.4
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Class 1 operation
The STA2500D supports operation at Class 1 output power levels with the use of an
external PA. The operation of the external PA and antenna switch are controlled by the
following signals:
Table 20.
If Class 1 functionality is enabled through SW parameter download, then these 6 control
signals are available on the pins as indicated in
Table 21.
Table 22.
Configuration 2 allows to deploy the STA2500D in Class 1 mode, still maintaining the
necessary control signals to coexist and cooperate with a WLAN transceiver. The
handshake between the STA2500D and a WLAN device happens in this case through other
BT_GPIO pins.
Power-up
The BT_RESETN pin should be active while powering up BT_VDD_HV and should stay
active at least two cycles of the low power clock (BT_LP_CLK) after power-up is completed.
The time between the STA2500D making BT_CLK_REQ_OUT_x active and the platform
providing a stable clock should maximally be 15 ms.
edr_mode
Control signal name
Function
edr_mode
PA_VAL0
PA_VAL1
Function
PA_VAL0
PA_VAL1
RXEN
AntSw
PAEN
AntSw
RXEN
PAEN
Output power: class 1 control signals
Output power: class 1 device pin configuration (depending on SW
parameter download)
Output power: class 1 device pin configuration (depending on SW
parameter download)
BT_CLK_REQ_OUT_1
SW configuration a
PA enable (active during TX slot)
Bit 0 of the power level delivered by the PA
Bit 1 of the power level delivered by the PA
LNA enable (if present)
Control of the antenna switch
Indication to PA whether TX is EDR or BR
Doc ID 16067 Rev 1
BT_HOST_WAKEUP
BT_GPIO_0
BT_CLK_REQ_IN_1
BT_CLK_REQ_IN_2
(BT_GPIO_11)
SW configuration 1
BT_CLK_REQ_OUT_2
SW configuration b
Table 21
Function
and
Table
BT_GPIO_16
BT_GPIO_10
BT_GPIO_9
BT_GPIO_8
BT_GPIO_11
SW configuration 2
22.
not available on a pin
SW configuration c
STA2500D