PIC12F1822 MICROCHIP [Microchip Technology], PIC12F1822 Datasheet - Page 72

no-image

PIC12F1822

Manufacturer Part Number
PIC12F1822
Description
8/14-Pin Flash Microcontrollers with nanoWatt XLP Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC12F1822-E/SN
Manufacturer:
ABILIS
Quantity:
15 400
Part Number:
PIC12F1822-E/SN
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
PIC12F1822-E/SN
0
Part Number:
PIC12F1822-I/MF
Manufacturer:
ALLEGRO
Quantity:
1 001
Part Number:
PIC12F1822-I/MF
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
PIC12F1822-I/P
Manufacturer:
MICROCHIP
Quantity:
1 200
Part Number:
PIC12F1822-I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
PIC12F1822-I/SN
Manufacturer:
MICROCHIP
Quantity:
4 500
Part Number:
PIC12F1822-I/SN
Manufacturer:
MICROCHI
Quantity:
1 700
Part Number:
PIC12F1822-I/SN
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
PIC12F1822-I/SN
0
Company:
Part Number:
PIC12F1822-I/SN
Quantity:
30 000
Part Number:
PIC12F1822T-I/MF
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
PIC12F1822T-I/SN
0
PIC12F/LF1822/16F/LF1823
REGISTER 6-1:
DS41413A-page 72
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4-3
bit 2-0
Note 1: In this mode, the 25% and 75% duty cycle accuracy will be dependent on the source clock duty cycle.
CLKREN
R/W-0/0
2: In this mode, the duty cycle will always be equal to the source clock duty cycle, unless a duty cycle of 0%
3: To route CLKR to pin, CLKOUTEN of Configuration Word 1 = 1 is required. CLKOUTEN of Configuration
is selected.
Word 1 = 0 will result in F
CLKREN: Reference Clock Module Enable bit
1 = Reference clock module is enabled
0 = Reference clock module is disabled
CLKROE: Reference Clock Output Enable bit
1 = Reference clock output is enabled on CLKR pin
0 = Reference clock output disabled on CLKR pin
CLKRSLR: Reference Clock Slew Rate Control limiting enable bit
1 = Slew rate limiting is enabled
0 = Slew rate limiting is disabled
CLKRDC<1:0>: Reference Clock Duty Cycle bits
11 = Clock outputs duty cycle of 75%
10 = Clock outputs duty cycle of 50%
01 = Clock outputs duty cycle of 25%
00 = Clock outputs duty cycle of 0%
CLKRDIV<2:0> Reference Clock Divider bits
111 = Base clock value divided by 128
110 = Base clock value divided by 64
101 = Base clock value divided by 32
100 = Base clock value divided by 16
011 = Base clock value divided by 8
010 = Base clock value divided by 4
001 = Base clock value divided by 2
000 = Base clock value
CLKROE
R/W-0/0
CLKRCON: REFERENCE CLOCK CONTROL REGISTER
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
CLKRSLR
R/W-1/1
OSC
(2)
/4. See Section 6.3 “Conflicts with the CLKR pin” for details.
CLKRDC1
R/W-1/1
Preliminary
(1)
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
CLKRDC0
(3)
R/W-0/0
CLKRDIV2
R/W-0/0
 2010 Microchip Technology Inc.
CLKRDIV1
R/W-0/0
CLKRDIV0
R/W-0/0
bit 0

Related parts for PIC12F1822