NG80960JA-16 INTEL [Intel Corporation], NG80960JA-16 Datasheet - Page 17

• Manufacturer Part Number: NG80960JA-16
• Description: EMBEDDED 32-BIT MICROPROCESSOR
• Manufacturer: INTEL [Intel Corporation]

Table 3.
Advance Information Datasheet
Pin Description — External Bus Signals (Sheet 1 of 3)
AD31:0
NAME
A3:2
ALE
ALE
ADS
TYPE
R(X)
P(Q)
R(X)
P(Q)
S(L)
H(Z)
R(0)
H(Z)
P(0)
R(1)
H(Z)
P(1)
R(1)
H(Z)
P(1)
H(Z)
I/O
O
O
O
O
ADDRESS / DATA BUS carries 32-bit physical addresses and 8-, 16- or 32-bit data
to and from memory. During an address (
address (bits 0-1 indicate SIZE; see below). During a data (T
data is present on one or more contiguous bytes, comprising AD31:24, AD23:16,
AD15:8 and AD7:0. During write operations, unused pins are driven to determinate
values.
SIZE, which comprises bits 0-1 of the AD lines during a
number of data transfers during the bus transaction.
When the processor enters Halt mode, if the previous bus operation was a:
Typically, AD1:0 reflect the SIZE information of the last bus transaction (either
instruction fetch or load/store) that was executed before entering Halt mode.
ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is
asserted during a
active HIGH and floats to a high impedance state during a hold cycle (T
ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is the
inverted version of ALE. This signal gives the 80960Jx a high degree of compatibility
with existing 80960Kx systems.
ADDRESS STROBE indicates a valid address and the start of a new bus access.
The processor asserts ADS for the entire
samples ADS at the end of the cycle.
ADDRESS3:2 comprise a partial demultiplexed address bus.
32-bit memory accesses: the processor asserts address bits A3:2 during
partial word address increments with each assertion of RDYRCV during a burst.
16-bit memory accesses: the processor asserts address bits A3:1 during
driven on the BE1 pin. The partial short word address increments with each
assertion of RDYRCV during a burst.
8-bit memory accesses: the processor asserts address bits A3:0 during
driven on BE1:0. The partial byte address increments with each assertion of
RDYRCV during a burst.
• write — AD31:2 are driven with the last data value on the AD bus.
• read — AD31:4 are driven with the last address value on the AD bus; AD3:2 are
AD1
0
0
1
1
driven with the value of A3:2 from the last data cycle.
AD0
0
1
0
1
Bus Transfers
1 Transfer
2 Transfers
3 Transfers
4 Transfers
T
a
cycle and deasserted before the beginning of the T
80960JA/JF/JD/JT 3.3 V Microprocessor
DESCRIPTION
T
T
a
a
) cycle, bits 31:2 contain a physical word
cycle. External bus control logic typically
T
a
cycle, specifies the
d
) cycle, read or write
T
h
d
a
).
T
T
, with A1:0
state. It is
a
a
. The
with A1
17