NG80960JA-16 INTEL [Intel Corporation], NG80960JA-16 Datasheet - Page 68

• Manufacturer Part Number: NG80960JA-16
• Description: EMBEDDED 32-BIT MICROPROCESSOR
• Manufacturer: INTEL [Intel Corporation]

80960JA/JF/JD/JT 3.3 V Microprocessor
5.1
Figure 43.
68
Basic Bus States
The bus has five basic bus states: idle (Ti), address (Ta), wait/data (Tw/Td), recovery (Tr), and hold
(Th). During system operation, the processor continuously enters and exits different bus states.
The bus occupies the idle (Ti) state when no address/data transactions are in progress and when RESET is
asserted. When the processor needs to initiate a bus access, it enters the Ta state to transmit the address.
Following a Ta state, the bus enters the Tw/Td state to transmit or receive data on the address/data
lines. Assertion of the RDYRCV input signal indicates completion of each transfer. When data is
not ready, the processor can wait as long as necessary for the memory or I/O device to respond.
After the data transfer, the bus exits the Tw/Td state and enters the recovery (Tr) state. In the case of a
burst transaction, the bus exits the Td state and re-enters the Td/Tw state to transfer the next data word.
The processor asserts the BLAST signal during the last Tw/Td states of an access. Once all data words
transfer in a burst access (up to four), the bus enters the Tr state to allow devices on the bus to recover.
The processor remains in the Tr state until RDYRCV is deasserted. When the recovery state
completes, the bus enters the Ti state if no new accesses are required. If an access is pending, the
bus enters the Ta state to transmit the new address.
Bus States with Arbitration
ONCE & RESET
DEASSERTION
Ti — IDLE STATE
Ta — ADDRESS STATE
Tw / Td — WAIT/DATA STATE
Tr — RECOVERY STATE
Th — HOLD STATE
To — ONCE STATE
AND (NO HOLD
NO REQUEST
OR LOCKED)
To
REQUEST PENDING
AND (NO HOLD OR
RESET
LOCKED)
Ti
Ta
PENDING AND
NOT LOCKED
REQUEST
NO HOLD
HOLD AND
AND NO HOLD
NO REQUEST
HOLD OR LOCKED)
PENDING AND (NO
RECOVERED AND
REQUEST PENDING — NEW TRANSACTION
NOT RECOVERED — RDYRCV ASSERTED
REQUEST
NO REQUEST — NO NEW TRANSACTION
NOT LOCKED — NO ATOMIC EXECUTION IN PROGRESS
RECOVERED — RDYRCV NOT ASSERTED
NOT READY — RDYRCV NOT ASSERTED
NO BURST — BLAST ASSERTED
NO HOLD — HOLD REQUEST NOT ASSERTED
LOCKED — ATOMIC EXECUTION (ATADD, ATMOD) IN PROGRESS
READY — RDYRCV ASSERTED
BURST — BLAST NOT ASSERTED
RESET — RESET ASSERTED
ONCE — ONCE ASSERTED
HOLD — HOLD REQUEST ASSERTED
Tw/Td
Th
HOLD
NO REQUEST AND
RECOVERED AND
(READY AND BURST)
(NO HOLD OR
OR NOT READY
LOCKED)
Advance Information Datasheet
READY AND NO BURST
RECOVERED AND
HOLD AND NOT
LOCKED
Tr
RECOVERED
NOT