NG80960JA-16 INTEL [Intel Corporation], NG80960JA-16 Datasheet - Page 47

• Manufacturer Part Number: NG80960JA-16
• Description: EMBEDDED 32-BIT MICROPROCESSOR
• Manufacturer: INTEL [Intel Corporation]

Table 24.
4.7.1
Figure 10.
Advance Information Datasheet
Note Definitions for Table 23, 80960Jx AC Characteristics (pg. 44)
AC Test Conditions and Derating Curves
The AC Specifications in Section 4.7, “AC Specifications” are tested with the 50 pF load indicated
in Figure 10. Figure 11 shows how timings and output rise and fall times vary with load
capacitance.
AC Test Load
NOTES:
10.Relative to falling edge of TCK.
11.Worst-case T
1. Not tested.
2. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter
3. Inactive ALE/ALE refers to the falling edge of ALE and the rising edge of ALE. For inactive ALE/ALE
4. A float condition occurs when the output current becomes less than I
5. AD31:0 are synchronous inputs. Setup and hold times must be met for proper processor operation. NMI
6. RDYRCV and HOLD are synchronous inputs. Setup and hold times must be met for proper processor
7. RESET may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a
8. ONCE and STEST must be stable at the rising edge of RESET for proper operation.
9. Guaranteed by design. May not be 100% tested.
designed to be no longer than the valid delay.
and XINT7:0 may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition
minimum of two CLKIN periods to guarantee recognition.
frequency spectrum should not have any power peaking between 500 KHz and 1/3 of the CLKIN
frequency.
timings, refer to Relative Output Timings in this table.
at a particular clock edge. For asynchronous operation, NMI and XINT7:0 must be asserted for a
operation.
particular clock edge.
low output state. The Address/Data Bus pins encounter this condition between the last access of a read,
and the address cycle of a following write. 5 V signals take 3 ns longer to discharge than 3.3 V signals at
50 pF loads.
OV
condition occurs on I/O pins when pins transition from a floating high input to driving a
Output Pin
C
L
80960JA/JF/JD/JT 3.3 V Microprocessor
C
L
= 50 pF for all signals
OL
. Float delay is not tested, but is
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