LAN91C100-FD-SS SMSC [SMSC Corporation], LAN91C100-FD-SS Datasheet - Page 53

• Manufacturer Part Number: LAN91C100-FD-SS
• Description: FEAST Fast Ethernet Controller with Full Duplex Capability
• Manufacturer: SMSC [SMSC Corporation]

EISA 32 BIT SLAVEEISA 32 bit slave
On EISA the LAN91C100FD is accessed as a 32 bit I/O slave, along with a Slave DMA type "C" data path option. As an
I/O slave, the LAN91C100FD uses asynchronous accesses. In creating nRD and nWR inputs, the timing information is
externally derived from nCMD edges. Given that the access will be at least 1.5 to 2 clocks (more than 180ns at least) there
is no need to negate EXRDY, simplifying the EISA interface implementation. As a DMA Slave, the LAN91C100FD accepts
burst transfers and is able to sustain the peak rate of one doubleword every BCLK. Doubleword alignment is assumed for
DMA transfers. Up to three extra bytes in the beginning and at the end of the transfer should be moved by the CPU using
I/O accesses to the Data Register. The LAN91C100FD will sample EXRDY and postpone DMA cycles if the memory cycle
solicits wait states.
SMSC DS – LAN91C100FD REV. B
combined with
combined with
Latched W-R
Latched W-R
nBE0 nBE1
nBE2 nBE3
EISA BUS
LA2-LA15
RESDRV
nSTART
SIGNAL
D0-D31
nCMD
nCMD
M/nIO
IRQn
AEN
LAN91C100FD
INTR0-INTR3
nBE0 n BE1
nBE2 nBE3
SIGNAL
D0-D31
A2-A15
RESET
nADS
nWR
AEN
nRD
Table 5 - EISA 32 Bit Slave Signal Connections
Address bus used for I/O space and register decoding, latched
by nADS (nSTART) trailing edge.
Qualifies valid I/O decoding - enabled access when low. These
signals are externally ORed. Internally the AEN pin is latched by
nADS rising edge and transparent while nADS is low.
I/O Read strobe - asynchronous read accesses. Address is valid
before its leading edge. Must not be active during DMA bursts if
DMA is supported.
I/O Write strobe - asynchronous write access. Address is valid
before leading edge . Data latched on trailing edge. Must not be
active during DMA bursts if DMA is supported.
Address strobe is connected to EISA nSTART.
Byte enables. Latched on nADS rising edge.
Interrupts used as active high edge triggered
32 bit data bus. The bus byte(s) used to access the device are a
function of nBE0-nBE3:
nBE0 nBE1 nBE2
Not used = tri-state on reads, ignored on writes. Note that nBE2
and nBE3 override the value of A1, which is tied low in this
application. Other combinations of nBE are not supported by the
LAN91C100FD. Software drivers are not anticipated to generate
them.
0
0
1
0
1
1
1
Page 53
0
0
1
1
0
1
1
0
1
0
1
1
0
1
nBE3
0
1
0
1
1
1
0
NOTES
Double word access
Low word access
High word access
Byte 0 access
Byte 1 access
Byte 2 access
Byte 3 access
Rev. 01-20-06