FDC37M81 SMSC [SMSC Corporation], FDC37M81 Datasheet - Page 153
FDC37M81
Manufacturer Part Number
FDC37M81
Description
PC98/99 Compliant Enhanced Super I/O Controller with Keyboard/Mouse Wake-Up
Manufacturer
SMSC [SMSC Corporation]
Datasheet
1.FDC37M81.pdf
(198 pages)
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Note 1: To properly share and IRQ,
Serial Port 1
Mode Register
Default = 0x00
on VCC POR, VTR
POR and HARD
RESET
Serial Port 2
Mode Register
Default = 0x00
on VCC POR, VTR
POR and HARD
RESET
NAME
NAME
1. Configure UART1 (or UART2) to use the desired IRQ pin.
2. Configure UART2 (or UART1) to use No IRQ selected.
3. Set the share IRQ bit.
Note: If both UARTs are configured to use different IRQ pins and the share IRQ bit is set,
then both of the UART IRQ pins will assert when either UART generates an interrupt.
Table 61 - Serial Port 2, Logical Device 5 [Logical Device Number = 0x05]
Table 60 - Serial Port 1, Logical Device 4 [Logical Device Number = 0x04]
REG INDEX
REG INDEX
0xF0 R/W
0xF0 R/W
UART Interrupt Operation Table
Bit[0] MIDI Mode
= 0
= 1
Bit[1] High Speed
= 0
= 1
Bit[6:2] Reserved, set to zero
Bit[7]: Share IRQ
=0 UARTS use different IRQs
=1 UARTS share a common IRQ
See Note 1 below.
Bit[0] MIDI Mode
= 0
= 1
Bit[1] High Speed
= 0
= 1
Bit[7:2] Reserved, set to zero
MIDI support disabled (default)
MIDI support enabled
High Speed Disabled(default)
High Speed Enabled
MIDI support disabled (default)
MIDI support enabled
High Speed disabled(default)
High Speed enabled
153
DEFINITION
DEFINITION
STATE
STATE
C
C