FDC37M81 SMSC [SMSC Corporation], FDC37M81 Datasheet - Page 68

no-image

FDC37M81

Manufacturer Part Number
FDC37M81
Description
PC98/99 Compliant Enhanced Super I/O Controller with Keyboard/Mouse Wake-Up
Manufacturer
SMSC [SMSC Corporation]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
FDC37M812
Manufacturer:
SMSC
Quantity:
1
Part Number:
FDC37M812
Manufacturer:
NEC
Quantity:
6 000
Part Number:
FDC37M812
Manufacturer:
SMSC
Quantity:
1 000
Part Number:
FDC37M812
Manufacturer:
SMSC
Quantity:
1 000
Part Number:
FDC37M812
Manufacturer:
SMSC
Quantity:
20 000
Part Number:
FDC37M813
Manufacturer:
FORTUNE
Quantity:
176
Part Number:
FDC37M813
Manufacturer:
SMSC
Quantity:
1 000
Part Number:
FDC37M817
Manufacturer:
SMSC
Quantity:
20 000
Part Number:
FDC37M817-MS
Manufacturer:
Microchip Technology
Quantity:
10 000
The FDC37M81x incorporates two full function
UARTs. They are compatible with the NS16450,
the 16450 ACE registers and the NS16C550A.
The
conversion on received characters and parallel-
to-serial conversion on transmit characters. The
data rates are independently programmable
from 460.8K baud down to 50 baud.
character options are programmable for 1 start;
1, 1.5 or 2 stop bits; even, odd, sticky or no
parity; and prioritized interrupts. The UARTs
each contain a programmable baud rate
generator that is capable of dividing the input
clock or crystal by a number from 1 to 65535.
The UARTs are also capable of supporting the
MIDI data rate. Refer to the Configuration
Registers for information on disabling, power
down and changing the base address of the
UARTs. The interrupt from a UART is enabled
by programming OUT2 of that
UARTS
*Note: DLAB is Bit 7 of the Line Control Register
DLAB*
X
X
X
X
X
X
X
0
0
0
1
1
perform
A2
0
0
0
0
0
0
1
1
1
1
0
0
Table 29 - Addressing the Serial Port
serial-to-parallel
A1
0
0
0
1
1
1
0
0
1
1
0
0
SERIAL PORT (UART)
A0
The
0
0
1
0
0
1
0
1
0
1
0
1
68
Receive Buffer (read)
Transmit Buffer (write)
Interrupt Enable (read/write)
Interrupt Identification (read)
FIFO Control (write)
Line Control (read/write)
Modem Control (read/write)
Line Status (read/write)
Modem Status (read/write)
Scratchpad (read/write)
Divisor LSB (read/write)
Divisor MSB (read/write
UART to a logic "1". OUT2 being a logic "0"
disables that UART's interrupt.
UART also supports IrDA 1.0, HP-SIR and ASK-
IR modes of operation.
Note: The UARTs may be configured to share
an interrupt. Refer to the Configuration section
for more information.
REGISTER DESCRIPTION
Addressing of the accessible registers of the
Serial Port is shown below.
addresses of the serial ports are defined by the
configuration
section). The Serial Port registers are located at
sequentially increasing addresses above these
base addresses. The FDC37M81x contains two
serial ports, each of which contain a register set
as described below.
REGISTER NAME
registers
(see
Configuration
The second
The base

Related parts for FDC37M81