UJA1061TW PHILIPS [NXP Semiconductors], UJA1061TW Datasheet - Page 28

• Manufacturer Part Number: UJA1061TW
• Description: Low speed CAN/LIN system basis chip
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
6.8.2
The UJA1061 handles and signals the following LIN-bus
related failures:
These failure events force an interrupt to the
microcontroller whenever the status changes and the
corresponding interrupt is enabled.
6.9
The INH output pin, which can be used as inhibit for an
extra (external) voltage regulator, is floating after the first
powering of the UJA1061. This ensures that yet-to-be
connected voltage regulators are switched off. The INH bit
in the corresponding SPI register can be accessed in
Normal mode, Flash mode and in Standby mode.
Whenever Restart, Sleep or Fail-safe mode is entered, the
INH bits are reset again, with pin INH floating as the result.
This is also true whenever undervoltage of V1 has been
detected, or an external reset edge is applied to the
UJA1061. Therefore, the application has to reactivate
external supplies in a failure situation or in the event of an
external reset.
The INH output pin can also be programmed as ‘limp
home’ output, which is also floating after power-up but is
activated by the UJA1061 in case the UJA1061 enters
Fail-safe mode. For fail-safe reasons, this ‘limp home’
behaviour of pin INH can be activated by setting the Limp
Home Mode (LHM) bit via the Special mode register. This
LHM bit can therefore be set only once after a first battery
connection before the watchdog is initialized, that is within
the 256 ms start-up period and before the first SPI write
access to any other register.
2004 Mar 22
LIN-bus clamped dominant; within Active mode the
termination switch at pin RTLIN is switched to the
internal weak current source; within Off-line RTLIN will
be floating
TXDL clamped dominant; the transmitter is disabled
LIN-bus clamped recessive; the transmitter is switched
off and the LIN transmitter off bit (LTO) is set.
Low speed CAN/LIN system basis chip
Inhibit output (pin INH)
B
US AND
TXDL
FAILURE DETECTION
28
6.10
The behaviour of pin WAKE depends on the sampled
level: a pull-down behaviour is activated when the pin is
pulled LOW, and a pull-up behaviour towards BAT42 is
activated when the pin is pulled HIGH externally.
The setting of the WAKE Sample Control bit (WSC)
defines the sample mode of the pin:
If V3 is continuously ON, pin WAKE input will be sampled
continuously also, regardless of the level of the bit WSC.
If the interrupt mode is selected, a negative edge on
pin WAKE sets pin INTN immediately to LOW. Reading
the corresponding interrupt register clears all bits. If the
reset mode is selected, the wake-up event forces a
hardware reset without interrupt. The reset source bits in
the System Status register reflect the source of the reset
event, while dedicated status bits, Edge WAKE Status
(EWS) and Level WAKE Status (LWS), within the same
register, offer information according the actual status of
pin WAKE. These two bits can be polled and read out also
when the interrupt option instead of the reset option has
been chosen.
Continuous sampling (with an internal clock) if the bit is
set logic 1
Sampling synchronised to the cyclic behaviour of V3 if
the bit is set logic 0 (see Fig.12). This is to save bias
current within external switches in low-power operation.
Two repetition times are possible: 16 and 32 ms.
Wake-up input (pin WAKE)
Objective specification
UJA1061