UJA1061TW PHILIPS [NXP Semiconductors], UJA1061TW Datasheet - Page 41

• Manufacturer Part Number: UJA1061TW
• Description: Low speed CAN/LIN system basis chip
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
6.14.6
This register allows the current setting of the interrupt enable bits to be read back.
Table 7 IEF - Interrupt Enable Feedback register (address 01) bit description
2004 Mar 22
Low speed CAN/LIN system basis chip
15, 14
BIT
13
12
11
10
9
8
7
6
5
4
3
2
1
0
I
NTERRUPT
SYMBOL
V2V3FIE V2/V3 Failure
CANFIE
BATFIE
SPIFIE
LINFIE
A1, A0
CANIE
WTIE
LINIE
GSIE
OTIE
RRS
WIE
RO
E
NABLE
register address
Read Register Select
Read Only
Watchdog Time-out
Interrupt Enable
Over-temperature
Interrupt Enable
Ground Shift Interrupt
Enable
SPI clock count
Failure Interrupt
Enable
BAT Failure Interrupt
Enable
Interrupt Enable
CAN failure Interrupt
Enable
LIN Failure Interrupt
Enable
Wake-up Interrupt
Enable
reserved
CAN interrupt enable
LIN interrupt enable
DESCRIPTION
F
EEDBACK REGISTER
VALUE
01
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
41
read Interrupt Enable Feedback register
read the Interrupt Enable Feedback register without writing
to Interrupt Enable register
read the Interrupt Enable Feedback register and write to
Interrupt Enable (previous content is reflected during read)
a watchdog overflow during Standby mode causes an
interrupt instead of a reset
no interrupt forced
exceeding or dropping below the temperature warning limit
causes an interrupt
no interrupt forced
exceeding or dropping below the GND shift limit causes an
interrupt
no interrupt forced
wrong number of CLK cycles (more than, or less than 16)
forces an interrupt; within Start-up and Restart mode, a
reset is performed instead of an interrupt
no interrupt forced, SPI access simply ignored if wrong
number of cycles is applied (more than, or less than 16)
falling edge at SENSE forces an interrupt
no interrupt forced
detection of a short circuit at V2 or V3 forces an interrupt
no interrupt forced
any change of the CAN failure status forces an interrupt
no interrupt forced
any change of the LIN failure status forces an interrupt
no interrupt forced
a negative edge at WAKE generates an interrupt in
Normal, Flash or Standby modes
a negative edge at WAKE generates a reset in Standby
mode
reserved for future use; should always be set to logic 0 in
order to secure compatibility with future functions which will
be activated by a logic 1
CAN-bus event results in a wake-up interrupt
CAN-bus event results in a reset
LIN-bus event results in a wake-up interrupt
LIN-bus event results in a reset
FUNCTION
Objective specification
UJA1061