ADT7473_11 ONSEMI [ON Semiconductor], ADT7473_11 Datasheet - Page 21

• Manufacturer Part Number: ADT7473_11
• Description: dbCOOL Remote Thermal Monitor and Fan Control
• Manufacturer: ONSEMI [ON Semiconductor]

bit has cleared, reset the corresponding interrupt mask bit
to 0. This causes the SMBALERT output and status bits to
behave as shown in Figure 30.
Masking Interrupt Sources
Register 0x74, Interrupt Mask Register 1
Register 0x75, Interrupt Mask Register 2
masked out to prevent SMBALERT interrupts. Masking an
interrupt source prevents only the SMBALERT output from
being asserted; the appropriate status bit is set normally.
Interrupt Mask Register 1 (0x74)
Interrupt Status Register 2, assuming all the mask bits in the
Interrupt Mask Register 2 (0x75) =1; SMBALERT is still
asserted.
Interrupt Status Register 2, assuming all the mask bits in the
Interrupt Mask Register 2 (0x75) =1; SMBALERT is not
asserted.
Bit 6 (R2T) = 1, masks SMBALERT for Remote 2
temperature
Bit 5 (LT) = 1, masks SMBALERT for local temperature.
Bit 4 (R1T) = 1, masks SMBALERT for Remote 1
temperature.
Bit 2 (V
Bit 1 (V
HIGH LIMIT
TEMPERATURE
STATUS BIT
SMBALERT
Figure 30. How Masking the Interrupt Source Affects
Periodically poll the status registers. If the interrupt status
These registers allow individual interrupt sources to be
Bit 7 (OOL) = 0, when one or more alerts are generated in
OOL=1, when one or more alerts are generated in
STICKY
3. Read the status registers to identify the interrupt
4. Mask the interrupt source by setting the
5. Take the appropriate action for a given interrupt
6. Exit the interrupt handler.
source.
appropriate mask bit in the interrupt mask registers
(Register 0x74 and Register 0x75).
source.
CC
CCP
) = 1, masks SMBALERT for V
) = 1, masks SMBALERT for V
SMBALERT Output
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
INTERRUPT
MASK BIT SET
(TEMP BELOW LIMIT)
CLEARED ON READ
(SMBALERT RE−ARMED)
INTERRUPT MASK BIT
CC
CCP
CLEARED
channel.
channel.
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21
Interrupt Mask Register 2 (Reg. 0x75)
Bit 7 (D2) = 1, masks SMBALERT for Diode 2 errors.
Bit 6 (D1) = 1, masks SMBALERT for Diode 1 errors.
Bit 5 (FAN4) = 1, masks SMBALERT for Fan 4 failure.
bit masks SMBALERT for a THERM event.
Bit 4 (FAN3) = 1, masks SMBALERT for Fan 3.
Bit 3 (FAN2) = 1, masks SMBALERT for Fan 2.
Bit 2 (FAN1) = 1, masks SMBALERT for Fan 1.
Bit 1 (OVT) = 1, masks SMBALERT for overtemperature
(exceeding THERM limits).
Enabling the SMBALERT Interrupt Output
Pin 5 or Pin 9 can be reconfigured as an SMBALERT output
to signal out−of−limit conditions. (SMBALERT function is
available only on Pin 9 of ADT7473−1.)
asserts when temperature rises 0.25°C above the THERM
limit for the selected remote channel. Due to a THERM
event, the fans spin at full speed. This can be disabled by
setting Bit 2 in Configuration Register 0x7D.
THERM limit for the selected zone, Remote Channel D1 or
Remote Channel D2, and Bit 0 in Status Register 2 is cleared.
By default on the ADT7473−1, the THERM limit is set as
136°C for Remote Channel 2 and 100°C for Remote
Channel 1.
Assigning THERM Functionality to a Pin
functions: SMBALERT, THERM, GPIO, and TACH4. The
user chooses the required functionality by setting Bit 0 and
Bit 1 of Configuration Register 4 (0x7D).
by setting Bit 1 of Configuration Register 3 (0x78).
Table 11. ADT7473 Configuring Pin 5 as
SMBALERT Output
Table 12.
Configuration Register 3
(Register 0x78)
If the TACH4 pin is being used as the THERM input, this
The SMBALERT interrupt function is disabled by default.
The ADT7473−1 THERM_LATCH function latches and
Pin 5 remains latched until temperature falls below
Pin 9 on the ADT7473/ADT7473−1 has four possible
Once Pin 9 is configured as THERM, it must be enabled
Bit 1
0
0
1
1
Register
Bit 0
1
0
1
0
[0] ALERT = 1
SMBusALERT
Function
Bit Setting
THERM
TACH4
GPIO