ADT7473_11 ONSEMI [ON Semiconductor], ADT7473_11 Datasheet - Page 69

• Manufacturer Part Number: ADT7473_11
• Description: dbCOOL Remote Thermal Monitor and Fan Control
• Manufacturer: ONSEMI [ON Semiconductor]

Table 48. Register 0x74 — Interrupt Mask Register 1 (Power−On Default = 0x00)
Table 49. Register 0x75 — Interrupt Mask Register 2 (Power−On Default <7:0> = 0x00)
Table 50. Register 0x76 — Extended Resolution Register 1 (Power−On Default = 0x00)
1. If this register is read, this register and the registers holding the MSB of each reading are frozen until read.
Table 51. Register 0x77 — Extended Resolution Register 2 (Power−On Default = 0x00)
1. If this register is read, this register and the registers holding the MSB of each reading are frozen until read.
Bit No.
Bit No.
Bit No.
Bit No.
[3:2]
[5:4]
[3:2]
[5:4]
[7:6]
[1]
[2]
[4]
[5]
[6]
[7]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Mnemonic
Mnemonic
Mnemonic
Mnemonic
TDM1
TDM2
LTMP
FAN1
FAN2
FAN3
V
V
OOL
OVT
V
R1T
R2T
F4P
V
D1
D2
LT
CCP
CCP
CC
CC
Read−only
Read−only
Read−only
Read−only
Read−only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
V
V
R1T = 1, masks SMBALERT for out−of−limit conditions on the Remote 1 temperature
channel.
LT = 1, masks SMBALERT for out−of−limit conditions on the local temperature channel.
R2T = 1, masks SMBALERT for out−of−limit conditions on the Remote 2 temperature
channel.
OOL = 0, then when one or more alerts are generated in Interrupt Status Register 2, assuming
all the mask bits in the Interrupt Mask Register 2 (0x75) = 1, SMBALERT are still asserted.
OOL = 1, then when one or more alerts are generated in Interrupt Status Register 2, assuming
all the mask bits in the Interrupt Mask Register 2 (0x75) = 1, SMBALERT are not asserted.
OVT = 1, masks SMBALERT for overtemperature THERM conditions.
FAN1 = 1, masks SMBALERT for a Fan 1 fault.
FAN2 = 1, masks SMBALERT for a Fan 2 fault.
FAN3 = 1, masks SMBALERT for a Fan 3 fault.
F4P = 1, masks SMBALERT for a Fan 4 fault. If the TACH4 pin is being used as the THERM
input, this bit masks SMBALERT for a THERM timer event.
D1 = 1, masks SMBALERT for a diode open or short on a Remote 1 channel.
D2 = 1, masks SMBALERT for a diode open or short on a Remote 2 channel.
V
V
Remote 1 temperature LSBs. Holds the 2 LSBs of the 10−bit Remote 1 temperature
measurement.
Local temperature LSBs. Holds the 2 LSBs of the 10−bit local temperature measurement.
Remote 2 temperature LSBs. Holds the 2 LSBs of the 10−bit Remote 2 temperature
measurement.
CCP
CC
CCP
CC
= 1, masks SMBALERT for out−of−limit conditions on the V
LSBs. Holds the 2 LSBs of the 10−bit V
= 1, masks SMBALERT for out−of−limit conditions on the V
LSBs. Holds the 2 LSBs of the 10−bit V
http://onsemi.com
69
Description
Description
Description
Description
CC
CCP
measurement.
measurement.
(Note 1)
(Note 1)
CC
CCP
channel.
channel.