FIN3385_12 FAIRCHILD [Fairchild Semiconductor], FIN3385_12 Datasheet - Page 18

• Manufacturer Part Number: FIN3385_12
• Description: Low-Voltage, 28-Bit, Flat-Panel Display Link Serializer / Deserializer
• Manufacturer: FAIRCHILD [Fairchild Semiconductor]

© 2003 Fairchild Semiconductor Corporation
FIN3385 / FIN3386 • Rev. 1.0.6
AC Loadings and Waveforms
Note:
25. Test setup considers no requirement for separation of RMS and deterministic jitter. Other hardware setups,
Note:
26. This jitter pattern is used to test the jitter response (clock out) of the device over the power supply range with
27. Switching input data TxIn0 to TxIn20 at 0.5MHz and the input clock is shifted to left -3ns and to the right +3ns
28. The ±3ns cycle-to-cycle input jitter is the static phase error between the two clock sources. Jumping between two
such as Wavecrest boxes, can be used if no M1 software is available, but the test methodology in Figure 24
should be followed.
worst jitter ±3ns (cycle-to-cycle) clock input. The specific test methodology is as follows:
when data is HIGH.
clock sources to simulate the worst-case of clock-edge jump (3ns) from graphical controllers. Cycle-to-cycle jitter
at TxCLKOut pin should be measured cross V
Figure 24. Timing Diagram of Transmitter Clock Input with Jitter
Figure 23. Transmitter Clock Out Jitter Measurement Setup
(Continued)
CC
range with 100mV noise (V
18
CC
noise frequency <2MHz).
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