XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 122

no-image

XIO2000AI

Manufacturer Part Number
XIO2000AI
Description
PCI Express to PCI Bus Translation Bridge
Manufacturer
TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XIO2000AIZHH
Manufacturer:
Texas Instruments
Quantity:
10 000
Part Number:
XIO2000AIZZZ
Manufacturer:
Texas Instruments
Quantity:
10 000
PCI Express Extended Configuration Space
5.21 VC Resource Capability Register (VC0)
112
31:24
22:16
13:8
BIT
7:0
23
15
14
SCPS155C
The VC resource capability register for VC0 provides information to software regarding the port and arbitration
schemes supported by the bridge. See Table 5−17 for a complete description of the register contents.
RESET STATE
RESET STATE
PORT_ARB_TBL_OFFSET
BIT NUMBER
BIT NUMBER
PCI Express extended register offset:
Register type:
Default value:
MAX_TIME_SLOTS
ADV_SWITCHING
REJECT_SNOOP
PORT_ARB_CAP
FIELD NAME
RSVD
RSVD
Table 5−17. VC Resource Capability Register (VC0) Description
31
15
0
0
30
14
0
0
ACCESS
29
13
R
R
R
R
R
R
R
0
0
28
12
0
0
Port arbitration table offset. This read-only field returns the value 00h to indicate that
no port arbitration table is required for this VC.
Reserved. Returns 0b when read.
Maximum time slots. This read-only field returns the value 000 0000b because there is
no support for time-based, WRR arbitration on this VC.
Reject snoop transactions. This bit only has meaningful context for root ports;
therefore, returns 0b when read.
Advanced packet switching. This read-only bit returns 0b to indicate that the use of this
VC is not limited to AS traffic.
Reserved. Returns 00 0000b when read.
Port arbitration capability. This 8-bit encoded field indicates support for the various
schemes that are supported for port (secondary PCI device) arbitration. The field is
encoded as follows:
Bit 0 = Hardware fixed arbitration (round-robin)
Bit 1 = WRR with 32 phases
Bit 2 = WRR with 64 phases
Bit 3 = WRR with 128 phases
Bit 4 = Time-based WRR with 128 phases
Bit 5 = WRR with 256 phases
Bits 6 and 7 = Reserved
The returned value of 01h indicates that only hardware-fixed, round-robin arbitration is
support for this VC.
27
11
0
0
26
10
0
0
160h
Read-only
0000 0001h
25
0
9
0
24
0
8
0
23
0
7
0
DESCRIPTION
22
0
6
0
21
0
5
0
April 2007 Revised October 2008
20
0
4
0
19
0
3
0
18
0
2
0
17
0
1
0
16
0
0
1

Related parts for XIO2000AI