XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 65
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XIO2000AI
Manufacturer Part Number
XIO2000AI
Description
PCI Express to PCI Bus Translation Bridge
Manufacturer
TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]
Datasheet
1.XIO2000AI.pdf
(159 pages)
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4.12 Secondary Bus Number Register
4.13 Subordinate Bus Number Register
4.14 Secondary Latency Timer Register
4.15 I/O Base Register
April 2007 Revised October 2008
BIT
7:4
3:0
This read/write register specifies the bus number of the PCI bus segment that the PCI interface is connected
to. The bridge uses this register to determine how to respond to a type 1 configuration transaction.
This read/write register specifies the bus number of the highest number PCI bus segment that is downstream
of the bridge. The bridge uses this register to determine how to respond to a type 1 configuration transaction.
This read/write register specifies the secondary bus latency timer for the bridge, in units of PCI clock cycles.
This read/write register specifies the lower limit of the I/O addresses that the bridge forwards downstream.
See Table 4−6 for a complete description of the register contents.
RESET STATE
RESET STATE
RESET STATE
RESET STATE
BIT NUMBER
BIT NUMBER
BIT NUMBER
BIT NUMBER
FIELD NAME
PCI register offset:
Register type:
Default value:
PCI register offset:
Register type:
Default value:
PCI register offset:
Register type:
Default value:
PCI register offset:
Register type:
Default value:
IOBASE
IOTYPE
ACCESS
7
0
7
0
7
0
7
0
RW
R
6
0
6
0
6
0
6
0
I/O base. Defines the bottom address of the I/O address range that determines when to forward I/O
transactions from one interface to the other. These bits correspond to address bits [15:12] in the
I/O address. The lower 12 bits are assumed to be 000h. The 16 bits corresponding to address bits
[31:16] of the I/O address are defined in the I/O base upper 16 bits register (offset 30h, see
Section 4.24).
I/O type. This field is read-only 1h indicating that the bridge supports 32-bit I/O addressing.
Table 4−6. I/O Base Register Description
5
0
5
0
5
0
5
0
19h
Read/Write
00h
1Ah
Read/Write
00h
1Bh
Read/Write
00h
1Ch
Read-only, Read/Write
01h
4
0
4
0
4
0
4
0
3
0
3
0
3
0
3
0
2
0
2
0
2
0
2
0
1
0
1
0
1
0
1
0
DESCRIPTION
0
0
0
0
0
0
0
1
Classic PCI Configuration Space
SCPS155C
55
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