XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 56

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

Feature/Protocol Descriptions
3.10.4
3.11 Advanced Error Reporting Registers
3.12 Data Error Forwarding Capability
46
PCI OFFSET
B0h
B1h
B2h
B3h
SCPS155C
The bridge provides a programming mechanism to control serial-bus devices through system software. The
programming is accomplished through a doubleword of PCI configuration space at offset B0h. Table 3−14 lists
the registers that program a serial-bus device through software.
To access the serial EEPROM through the software interface, the following steps are performed:
1. The control and status byte is read to verify the EEPROM interface is enabled (SBDETECT asserted) and
2. The serial-bus word address is loaded. If the access is a write, then the data byte is also loaded.
3. The serial-bus slave address and R/W command selector byte is written.
4. REQBUSY is monitored until this bit is deasserted.
5. SB_ERR is checked to verify that the serial-bus operation completed without error. If the operation is a
In the extended PCI Express configuration space, the bridge supports the advanced error reporting
capabilities structure. For the PCI Express interface, both correctable and uncorrectable error status is
provided. For the PCI bus interface, secondary uncorrectable error status is provided. All uncorrectable status
bits have corresponding mask and severity control bits. For correctable status bits, only mask bits are
provided.
Both the primary and secondary interfaces include first error pointer and header log registers. When the first
error is detected, the corresponding bit position within the uncorrectable status register is loaded into the first
error pointer register. Likewise, the header information associated with the first failing transaction is loaded
into the header log. To reset this first error control logic, the corresponding status bit in the uncorrectable status
register is cleared by a writeback of 1b.
For systems that require high data reliability, ECRC is fully supported on the PCI Express interface. The
primary side advanced error capabilities and control register has both ECRC generation and checking enable
control bits. When the checking bit is asserted, all received TLPs are checked for a valid ECRC field. If the
generation bit is asserted, then all transmitted TLPs contain a valid ECRC field.
The bridge supports the transfer of data errors in both directions.
If a downstream PCI Express transaction with a data payload is received that targets the PCI bus and the EP
bit is set indicating poisoned data, then the bridge must ensure that this information is transferred to the PCI
bus. To do this, the bridge forces a parity error on each PCI bus data phase by inverting the parity bit calculated
for each double-word of data.
Accessing Serial-Bus Devices Through Software
not busy (REQBUSY and ROMBUSY deasserted).
read, then the serial-bus data byte is now valid.
Serial-bus data
(see Section 4.55)
Serial-bus word address
(see Section 4.56)
Serial-bus slave address
(see Section 4.57)
Serial-bus control and status
(see Section 4.58)
REGISTER NAME
Table 3−14. Registers Used To Program Serial-Bus Devices
Contains the data byte to send on write commands or the received data byte on read
commands.
The content of this register is sent as the word address on byte writes or reads. When bit 7
(PROT_SEL) in the serial-bus control and status register (offset B3h, see Section 4.58) is set
to 1b and the quick command protocol is selected, this word address is ignored.
Write transactions to this register initiate a serial-bus transaction. The slave device address
and the R/W command selector are programmed through this register.
Serial interface enable, busy, and error status are communicated through this register. In
addition, the protocol-select (PROT_SEL) bit and serial-bus test (SBTEST) bit are
programmed through this register.
DESCRIPTION
April 2007 Revised October 2008