XIO2000AI TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS], XIO2000AI Datasheet - Page 98

• Manufacturer Part Number: XIO2000AI
• Description: PCI Express to PCI Bus Translation Bridge
• Manufacturer: TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]

Classic PCI Configuration Space
4.68 Clock Run Status Register
† This bit is reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
88
BIT
7:1
0†
SCPS155C
The clock run status register indicates the state of the PCI clock-run features in the bridge. See Table 4−42
for a complete description of the register contents.
RESET STATE
BIT NUMBER
SEC_CLK_STATUS
PCI register offset:
Register type:
Default value:
FIELD NAME
RSVD
7
0
ACCESS
Table 4−42. Clock Run Status Register Description
RU
6
0
R
5
0
Reserved. Returns 000 0000b when read.
Secondary clock status. This bit indicates the status of the PCI bus secondary clock outputs.
DAh
Read-only
00h
0 = Secondary clock running
1 = Secondary clock stopped
4
0
3
0
2
0
1
0
0
0
DESCRIPTION
April 2007 Revised October 2008