HD6432160 RENESAS [Renesas Technology Corp], HD6432160 Datasheet - Page 187

• Manufacturer Part Number: HD6432160
• Description: Hitachi 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 7.4
7.5.4
Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed
consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB,
which define data transfers, can be set independently.
Figure 7.8 shows the overview of chain transfer operation. When activated, the DTC reads the
register information start address stored at the DTC vector address, and then reads the first register
information at that start address. After the data transfer, the CHNE bit will be tested. When it has
been set to 1, DTC reads the next register information located in a consecutive area and performs
the data transfer. These sequences are repeated until the CHNE bit is cleared to 0.
Name
DTC source address register
DTC destination address register
DTC transfer count register AH
DTC transfer count register AL
DTC transfer count register B
DAR
SAR
or
Chain Transfer
Register Functions in Block Transfer Mode
Figure 7.7 Memory Mapping in Block Transfer Mode
N th block
1st block
•
•
•
SAR
Abbreviation
DAR
CRAH
CRAL
CRB
Transfer
Block area
Function
Transfer source address
Transfer destination address
Holds block size
Block size counter
Transfer counter
Rev. 2.0, 08/02, page 147 of 788
DAR
SAR
or