HD6432160 RENESAS [Renesas Technology Corp], HD6432160 Datasheet - Page 190

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HD6432160

Manufacturer Part Number
HD6432160
Description
Hitachi 16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
7.5.7
Table 7.5 lists the execution status for a single DTC data transfer, and table 7.6 shows the number
of states required for each execution status.
Table 7.5
N:
Table 7.6
The number of execution states is calculated from using the formula below. Note that
of all transfers activated by one activation source (the number in which the CHNE bit is set to 1,
plus 1).
Rev. 2.0, 08/02, page 150 of 788
Mode
Normal
Repeat
Block transfer
Object to be Accessed
Bus width
Access states
Execution
status
Block size (initial setting of CRAH and CRAL)
Number of execution states = I · S
Number of DTC Execution States
Vector read S
Register
information
read/write S
Byte data read
S
Word data read
S
Byte data write
S
Word data
write S
Internal
operation S
K
K
L
DTC Execution Status
Number of States Required for Each Execution Status
Vector Read
I
1
1
1
L
M
J
I
On-Chip
RAM
32
1
1
1
1
1
1
Register Information
Read/Write
J
6
6
6
1
1
1
1
1
1
On-Chip
ROM
16
I
+
On-Chip I/O
Registers
2
4
2
4
8
2
(J · S
J
16
2
2
2
2
2
+ K · S
Data Read
K
1
1
N
K
1
+ L · S
2
4
2
4
2
4
L
Data Write
L
1
1
N
) + M · S
8
External Devices
3
6 + 2m
3 + m
6 + 2m
3 + m
6 + 2m
M
2
2
2
2
2
2
Internal
Operations
M
3
3
3
is the sum
16
3 + m
3 + m
3 + m
3 + m
3 + m
3

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