HD6432160 RENESAS [Renesas Technology Corp], HD6432160 Datasheet - Page 495

• Manufacturer Part Number: HD6432160
• Description: Hitachi 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 16.9 I
Item
SCL output cycle time
SCL output high pulse width
SCL output low pulse width
SDA output bus free time
Start condition output hold time
Retransmission start condition output
setup time
Stop condition output setup time
Data output setup time (master)
Data output setup time (slave)
Data output hold time
Note:* 6t
4. SCL and SDA inputs are sampled in synchronization with the internal clock. The AC timing
5. The I
Table 16.10 Permissible SCL Rise Time (t
IICX
0
1
therefore depends on the system clock cycle t
Characteristics. Note that the I
system clock frequency of less than 5 MHz.
speed mode). In master mode, the I
one bit at a time during communication. If t
the time determined by the input clock of the I
extended. The SCL rise time is determined by the pull-up resistance and load capacitance of
the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance
and load capacitance so that the SCL rise time does not exceed the values given in table 16.10.
t
Indication
7.5 t
17.5 t
cyc
2
cyc
C bus interface specification for the SCL rise time t
cyc
when IICX is 0, 12t
cyc
2
C Bus Timing (SCL and SDA Outputs)
Standard mode
High-speed mode 300
Standard mode
High-speed mode 300
cyc
when 1.
2
C bus interface AC timing specifications will not be met with a
I
Specification
(Max.)
1000
1000
2
C Bus
2
C bus interface monitors the SCL line and synchronizes
Symbol
t
t
t
t
t
t
t
t
t
SCLO
SCLHO
SCLLO
BUFO
STAHO
STASO
STOSO
SDASO
SDAHO
sr
) Values
sr
(the time for SCL to go from low to V
cyc
2
C bus interface, the high period of SCL is
, as shown in section 28, Electrical
ø =
5 MHz
1000
300
100
300
1t
Output Timing
28t
0.5t
0.5t
0.5t
0.5t
1t
0.5t
1t
3t
SCLO
SCLLO
SCLL
cyc
Time Indication
cyc
SCLO
SCLO
SCLO
SCLO
SCLO
– (6t
to 256t
sr
ø =
8 MHz
– 3t
937
300
1000
300
– 1t
– 1t
+ 2t
is 1000 ns or less (300 ns for high-
cyc
cyc
Rev. 2.0, 08/02, page 455 of 788
cyc
cyc
cyc
or 12t
cyc
ø =
10 MHz
750
300
1000
300
cyc
*)
[ns]
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ø =
16 MHz
468
300
1000
300
Notes
28.29.
See figure
IH
) exceeds
ø =
20 MHz
375
300
875
300