HD6432160 RENESAS [Renesas Technology Corp], HD6432160 Datasheet - Page 423

• Manufacturer Part Number: HD6432160
• Description: Hitachi 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Transmission: During transmission, the output signals from the SCI (UART frames) are
converted to IR frames using the IrDA interface (see figure 15.22).
For serial data of level 0, a high-level pulse having a width of 3/16 of the bit rate (1-bit interval) is
output (initial setting). The high-level pulse can be selected using the IrCKS2 to IrCKS0 bits in
KBCOMP.
The high-level pulse width is defined to be 1.41 s at minimum and (3/16 + 2.5%)
(3/16
MHz, a high-level pulse width of at least 1.4 µs to 1.6 µs can be specified.
For serial data of level 1, no pulses are output.
Reception: During reception, IR frames are converted to UART frames using the IrDA interface
before inputting to SCI_2.
Data of level 0 is output each time a high-level pulse is detected and data of level 1 is output when
no pulse is detected in a bit cycle. If a pulse has a high-level width of less than 1.41 s, the
minimum width allowed, the pulse is recognized as level 0.
High-Level Pulse Width Selection: Table 15.10 shows possible settings for bits IrCKS2 to
IrCKS0 (minimum pulse width), and this LSI's operating frequencies and bit rates, for making the
pulse width shorter than 3/16 times the bit rate in transmission.
bit rate) + 1.08 s at maximum. For example, when the frequency of system clock ø is 20
Transmission
Figure 15.22 IrDA Transmission and Reception
Start
bit
Bit
cycle
Start
bit
0
0
1
1
0
0
UART frame
IR frame
1
1
0
0
Data
Data
0
0
Reception
1
1
Pulse width is 1.6 s to
3/16 bit cycle
1
Rev. 2.0, 08/02, page 383 of 788
1
0
0
Stop
bit
Stop
bit
1
1
bit rate or