HD6432160 RENESAS [Renesas Technology Corp], HD6432160 Datasheet - Page 194

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HD6432160

Manufacturer Part Number
HD6432160
Description
Hitachi 16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
7.8
7.8.1
DTC operation can be enabled or disabled by the module stop control register (MSTPCR). In the
initial state, DTC operation is enabled. Access to DTC registers are disabled when module stop
mode is set. Note that when the DTC is being activated, module stop mode cannot be specified.
For details, refer to section 26, Power-Down Modes.
7.8.2
MRA, MRB, SAR, DAR, CRA, and CRB are all located in on-chip RAM. When the DTC is used,
the RAME bit in SYSCR should not be cleared to 0.
7.8.3
For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR, for reading and
writing. Multiple DTC activation sources can be set at one time (only at the initial setting) by
masking all interrupts and writing data after executing a dummy read on the relevant register.
7.8.4
Set the MSTP14 bit in MSTPCRH to 1 to make the DTC enter module stop mode, then confirm
that is set to 1 before making a transition to subactive mode or watch mode.
7.8.5
Interrupt sources of the SCI, IIC, LPC, or A/D converter which activate the DTC are cleared when
DTC reads from or writes to the respective registers, and they cannot be cleared by the DISEL bit
in MRB.
Rev. 2.0, 08/02, page 154 of 788
Usage Notes
Module Stop Mode Setting
On-Chip RAM
DTCE Bit Setting
Setting Required on Entering Subactive Mode or Watch Mode
DTC Activation by Interrupt Sources of SCI, IIC, LPC, or A/D Converter

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